SLVSDG8B April   2016  – June 2017 TPS25740 , TPS25740A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 VBUS Capacitance
      2. 8.1.2 USB Data Communications
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB Type-C CC Logic (CC1, CC2)
      2. 8.3.2  USB PD BMC Transmission (CC1, CC2, VTX)
      3. 8.3.3  USB PD BMC Reception (CC1, CC2)
      4. 8.3.4  Discharging (DSCG, VPWR)
        1. 8.3.4.1 Discharging after a Fault (VPWR)
      5. 8.3.5  Configuring Voltage Capabilities (HIPWR, EN9V, EN12V)
      6. 8.3.6  Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
      7. 8.3.7  Gate Driver (GDNG, GDNS)
      8. 8.3.8  Fault Monitoring and Protection
        1. 8.3.8.1 Over/Under Voltage (VBUS)
        2. 8.3.8.2 Over-Current Protection (ISNS, VBUS)
        3. 8.3.8.3 System Fault Input (GD, VPWR)
      9. 8.3.9  Voltage Control (CTL1, CTL2)
      10. 8.3.10 Sink Attachment Indicator (UFP, DVDD)
      11. 8.3.11 Power Supplies (VAUX, VDD, VPWR, DVDD)
      12. 8.3.12 Grounds (AGND, GND)
      13. 8.3.13 Output Power Supply (DVDD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Checking VBUS at Start Up
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 System-Level ESD Protection
      2. 9.1.2 Use of GD Internal Clamp
      3. 9.1.3 Resistor Divider on GD for Programmable Start Up
      4. 9.1.4 Selection of the CTL1 and CTL2 Resistors (R(FBL1) and R(FBL2))
      5. 9.1.5 Voltage Transition Requirements
      6. 9.1.6 VBUS Slew Control using GDNG C(SLEW)
      7. 9.1.7 Tuning OCP Using RF and CF
    2. 9.2 Typical Application , A/C Power Source (Wall Adapter)
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Pin Bypass Capacitors
        2. 9.2.2.2 Non-Configurable Components
        3. 9.2.2.3 Configurable Components
      3. 9.2.3 Application Curves
      4. 9.2.4 Typical Application, D/C Power Source
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Power Pin Bypass Capacitors
          2. 9.2.4.2.2 Non-Configurable Components
          3. 9.2.4.2.3 Configurable Components
        3. 9.2.4.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 D/C Power Source (Power Hub)
      2. 9.3.2 A/C Power Source (Wall Adapter)
      3. 9.3.3 Dual-Port Power Managed A/C Power Source (Wall Adaptor)
      4. 9.3.4 D/C Power Source (Power Hub with 3.3 V Rail)
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VPWR
  11. 11Layout
    1. 11.1 Port Current Kelvin Sensing
    2. 11.2 Layout Guidelines
      1. 11.2.1 Power Pin Bypass Capacitors
      2. 11.2.2 Supporting Components
    3. 11.3 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Port Current Kelvin Sensing

Figure 67 provides a routing example for accurate current sensing for the overcurrent protection feature. The sense amplifier measurement occurs between the ISNS and VBUS pins of the device. Improper connection of these pins can result in poor OCP performance.

TPS25740 TPS25740A Kelvin_Sense_Layout.gif Figure 67. Kelvin Sense Layout Example

11.2 Layout Guidelines

11.2.1 Power Pin Bypass Capacitors

  • C(VPWR): Place close to pin 20 (VPWR) and connect with low inductance traces and vias according to Figure 68.
  • C(VDD): Place close to pin 17 (VDD) and connect with low inductance traces and vias according to Figure 68.
  • C(DVDD): Place close to pin 13 (DVDD) and connect with low inductance traces and vias according to Figure 68.
  • C(VAUX): Place close to pin 16 (VAUX) and connect with low inductance traces and vias according to Figure 68.
  • C(VTX): Place close to pin 1 (VTX) and connect with low inductance traces and vias according to Figure 68.

11.2.2 Supporting Components

  • C(RX): Place C(RX1) and C(RX2) in line with the CC1 and CC2 traces as shown in Figure 23. These should be placed within one inch from the Type C connector. Minimize stubs and tees from on the trace routes.
  • Q1: Place Q1 in a manner such that power flows uninterrupted from Q1 drain to the Type C connector VBUS connections. Provide adequate copper plane from Q1 drain and source to the interconnecting circuits.
  • RS: Place RS as shown in Figure 68 to facilitate uninterrupted power flow to the Type C connector. Orient RS for optimal Kelvin sense connection/routing back to the TPS25740 or TPS25740A. In high current applications where the power dissipation is over 250 mW, provide an adequate copper feed to the pads of RS.
  • RG: Place RG near Q1 as shown in Figure 68. Minimize stray leakage paths as the GDNG sourcing current could be affected.
  • R(SLEW)/C(SLEW): Place R(SLEW) and C(SLEW) near RG as shown in Figure 68.
  • R(DSCG): Place on top of the VBUS copper route and connect to the DSCG pin with a 15 mil trace.
  • RF/CF: When required, place RF and CF as shown in Figure 68 to facilitate the Kelvin sense connection back to the device.
  • C(VBUS)/D(VBUS): Place C(VBUS) and D(VBUS) within one inch of the Type C connector and connect them to VBUS and GND using adequate copper shapes.
  • R(SEL)/R(PCTRL): Place R(SEL) and R(PCTRL) near the device.

11.3 Layout Example

The basic component placement and layout is provided in Figure 68. This layout represents the circuit shown in Figure 36. The layout for other power configurations will vary slightly from that shown below.

TPS25740 TPS25740A Layout_Example.gif Figure 68. Example Layout