JAJSHI6 データシート

JAJSHI6G June 2018 – July 2021 TPS25830-Q1 , TPS25831-Q1

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RHB|32
- MPQF130D

サーマルパッド・メカニカル・データ

RHB|32
- QFND592

発注情報

8.5 Electrical Characteristics

Limits apply over the junction temperature (T_J) range of -40°C to +150°C; V_IN = 13.5 V, f_SW =400 kHz, C_VCC = 2.2 µF, R_SNS = 15 mΩ, R_IMON = 13 kΩ, R_ILIMIT= 13 kΩ, R_SET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTATE (IN PIN)
V_IN	Operating input voltage range		4.5		36	V
I_Q	Operating quiescent current (non switching)	V_EN/UVLO = V_IN, CTRL1 = CTRL2 = V_CC, V_CSN = 8V, CC1 or CC2 = R_D, CC2 or CC1 = open		700	990	µA
I_Q-SB	Standby quiescent current	V_EN/UVLO = V_IN, CTRL1 = CTRL2 = V_CC, CC1 and CC2 = open			290	µA
I_SD	Shutdown quiescent current; measured at IN pin.	EN= 0		10	16	µA
ENABLE and UVLO (EN/UVLO PIN)
V_{EN/UVLO_VCC_H}	EN/UVLO input level required to turn on internal LDO	V_EN/UVLO rising threshold			1.14	V
V_{EN/UVLO_VCC_L}	EN/UVLO input level required to turn off internal LDO	V_EN/UVLO falling threshold	0.3			V
V_{EN/UVLO_H}	EN/UVLO input level required to turn on state machine	V_EN/UVLO rising threshold	1.140	1.200	1.260	V
V_{EN/UVLO_HYS}	Hysteresis	V_EN/UVLO falling threshold		90		mV
I_{LKG_EN/UVLO}	Enable input leakage current	V_EN/UVLO = 3.3 V		0.5		uA
INTERNAL LDO
V_{BOOT_UVLO}	Bootstrap voltage UVLO threshold			2.2		V
V_CC	Internal LDO output voltage appearing on VCC pin	6 V ≤ V_IN ≤ 36 V	4.75	5	5.25	V
V_{CC_UVLO_R}	Rising UVLO threshold		3.4	3.6	3.8	V
V_{CC_UVLO_HYS}	Hysteresis			600		mV
CURRENT LIMIT VOLTAGE (CSP - CSN/OUT PINS) TO ACTIVATE BUCK AVG CURRENT LIMITING
(V_CSP – V_CSN/OUT)	Current limit voltage buck regulator control loop	V_CSN = 5 V, R_SET = 300 Ω, R_ILIMIT = 13 kΩ, R_IMON = 13 kΩ, -40°C ≤ T_J ≤ 125°C	43.5	46	48.5	mV
(V_CSP – V_CSN/OUT)	Current limit voltage buck regulator control loop	V_CSN = 5 V, R_SET = 300 Ω, R_ILIMIT = 13 kΩ, R_IMON = 13 kΩ, -40°C ≤ T_J ≤ 150°C	42.5	46	49.5	mV
(V_CSP – V_CSN/OUT)	Current limit voltage buck regulator control loop	V_CSN = 5 V, R_SET = 300 Ω, R_ILIMIT = 26.1 kΩ, R_IMON = 13 kΩ, -40°C ≤ T_J ≤ 125°C	20	22.5	25	mV
(V_CSP – V_CSN/OUT)	Current limit voltage buck regulator control loop	V_CSN = 5 V, R_SET = 300 Ω, R_ILIMIT = 26.1 kΩ, R_IMON = 13 kΩ, -40°C ≤ T_J ≤ 150°C	19	22.5	26	mV
CURRENT LIMIT VOLTAGE (CSP - CSN/OUT PINS) TO ACTIVATE EXTERNAL NFET CURRENT LIMITING
(V_CSP – V_CSN/OUT)	Current limit voltage NFET control loop	V_CSN = 5 V, R_SET = 300 Ω, R_ILIMIT = 6.8 kΩ, R_IMON = 13 kΩ, -40°C ≤ T_J ≤ 125°C	40	43	46	mV
(V_CSP – V_CSN/OUT)	Current limit voltage NFET control loop	V_CSN = 5 V, R_SET = 300 Ω, R_ILIMIT = 6.8 kΩ, R_IMON = 13 kΩ, -40°C ≤ T_J ≤ 150°C	38.5	43	47.5	mV
(V_CSP – V_CSN/OUT)	Current limit voltage NFET control loop	V_CSN = 5 V, R_SET = 300 Ω, R_ILIMIT = 13.7 kΩ, R_IMON = 13 kΩ, -40°C ≤ T_J ≤ 125°C	18	21	24	mV
(V_CSP – V_CSN/OUT)	Current limit voltage NFET control loop	V_CSN = 5 V, R_SET = 300 Ω, R_ILIMIT = 13.7 kΩ, R_IMON = 13 kΩ, -40°C ≤ T_J ≤ 150°C	17	21	25	mV
CURRENT LIMIT - BUCK REGULATOR PEAK CURRENT LIMIT
I_L-SC-HS	High-side current limit		4.6	5.4	6.2	A
I_L-SC-LS	Low-side current limit		3.5	4	4.5	A
I_L-NEG-LS	Low-side negative current limit		–3.1	–2.1	–1.3	A
CABLE COMPENSATION VOLTAGE
V_IMON	Cable compensation voltage	(V_CSP – V_CSN) = 46 mV, R_SET = 300 Ω, R_ILIMIT = 13 kΩ, R_IMON = 13 kΩ	0.935	1	1.065	V
V_IMON	Cable compensation voltage	(V_CSP – V_CSN) = 23 mV, R_SET = 300 Ω, R_ILIMIT = 13 kΩ, R_IMON = 13 kΩ	0.435	0.5	0.565	V
V_IMON	Cable compensation voltage (internal clamp)	(V_CSP –V_CSN) = 46 mV, R_SET = 300 Ω, R_ILIMIT = 13 kΩ, R_IMON = open		1.8		V
BUCK OUTPUT VOLTAGE (CSN/OUT PIN)
V_CSN/OUT	Output voltage	CC1 or CC2 pulldown resistance = R_d, R_IMON = 0 Ω, R_ILIMIT = 0 Ω	5.05	5.10	5.15	V
V_CSN/OUT	Output voltage accuracy	CC1 or CC2 pulldown resistance = R_d, R_IMON = 0 Ω, R_ILIMIT = 0 Ω	–1		1	%
V_{CSN/OUT_OV}	Overvoltage level on CSN/OUT pin which buck regulator stops switching	V_CSN/OUT rising	7.1	7.5	7.9	V
V_{CSN/OUT_OV_HYS}	Hysteresis			500		mV
V_HC	CSN / OUT pin voltage required to trigger short circuit hiccup mode			2		V
V_DROP	Dropout voltage ( V_IN-V_OUT)	V_IN = V_OUT+ V_DROP,V_OUT= 5.1V, I_OUT = 3A		150		mV
BUCK REGULATOR INTERNAL RESISTANCE
R_DS-ON-HS	High-side MOSFET ON-resistance	Load = 3 A, T_J = 25°C		40	45	mΩ
R_DS-ON-HS	High-side MOSFET ON-resistance	Load = 3 A, -40°C ≤ T_J ≤ 125°C		40	68	mΩ
R_DS-ON-HS	High-side MOSFET ON-resistance	Load = 3 A, -40°C ≤ T_J ≤ 150°C		40	75	mΩ
R_DS-ON-LS	Low-side MOSFET ON-resistance	Load = 3 A, T_J = 25C		35	41	mΩ
R_DS-ON-LS	Low-side MOSFET ON-resistance	Load = 3 A, -40°C ≤ T_J ≤ 125°C		35	60	mΩ
R_DS-ON-LS	Low-side MOSFET ON-resistance	Load = 3 A, -40°C ≤ T_J ≤ 150°C		35	68	mΩ
NFET GATE DRIVE (LS_GD PIN)
V_{LS_GD}	NFET gate drive output voltage	V_CSN/OUT = 5.1 V, C_G = 1000 pF (see Figure 9-4)	9.5	11	12.5	V
I_{LS_DR_SRC}	NFET gate drive output source current	V_CSN/OUT = 5.1 V, C_G = 1000 pF	2	3	4	µA
I_{LS_DR_SNK}	NFET gate drive output sink current	V_CSN/OUT = 5.1 V, C_G = 1000 pF	20	35	50	µA
V_{LS_GD_UVLO_R}	V_CSN/OUT rising threshold for LS_GD operation	V_CSN/OUT rising	2.85	3	3.15	V
V_{LS_GD_UVLO_HYS}	Hysteresis			80		mV
BUS DISCHARGE (BUS PIN)
R_{BUS_DCHG}	BUS discharge resistance	V_BUS = 4 V	250	320	550	Ω
V_{BUS_NO_DCHG}	Falling threshold for VBUS not discharged				0.8	V
R_{BUS_DCHG_BLEED}	BUS bleed resistance	V_BUS = 4 V, No sink termination on CC lines, Time > t_{W_BUS_DCHG}	100	130	200	kΩ
V_{BUS_OV}	Rising threshold for BUS pin overvoltage protection	V_BUS rising	6.6	7	7.3	V
V_{BUS_OV_HYS}	Hysteresis			180		mV
R_{BUS_DCHG_18V}	Discharge resistance for BUS	V_BUS = 18V, measure leakage current		29		kΩ
R_{BUS_DCHG_8V}	Discharge resistance for BUS	V_BUS = 8V, measure leakage current		35		kΩ
CC1 AND CC2 - VCONN POWER SWITCH (CC1 AND CC2 PINS)
R_DS-ON	On-state resistance	I_CCn = 250 mA, T_J = 25°C		500	540	mΩ
R_DS-ON	On-state resistance	I_CCn = 250 mA, –40°C ≤ T_J ≤ 125°C,		500	830	mΩ
R_DS-ON	On-state resistance	I_CCn = 250 mA, –40°C ≤ T_J ≤ 150°C,		500	920	mΩ
I_{OS_CCn}	VCONN short circuit current limit	Short circuit current limit	350	430	550	mA
R_{VCONN_DCHG}	Discharge resistance	CC pin that was providing V_CONN before detach: V_CCX = 4V	650	850	1100	Ω
V_TH	Falling threshold for discharged	CC pin that was providing V_CONN before detach	570	600	630	mV
V_TH	Discharged threshold hysteresis			100		mV
V_{CCx_OV}	Rising threshold for CCn pin overvoltage protection	CC pin voltage V_CCn rising	5.8	6.1	6.4	V
V_{CCx_OV_HYS}	Hysteresis			150		mV
R_{CCn_DCHG_18V}	Discharge resistance for CCn	CC pin voltage V_CCn = 18V, measure leakage current		40		kΩ
R_{CCn_DCHG_8V}	Discharge resistance for CCn	CC pin voltage V_CCn = 8V, measure leakage current		86		kΩ
CC1/CC2 CONNECT MANAGEMENT: DANGLING ELECTRONICALLY MARKED CABLE MODE
I_{SRC_CCn}	Sourcing current on the passthrough CC line	CC pin voltage 0 V ≤ V_CCn ≤ 1.5 V	64	80	96	µA
I_{SRC_CCn}	Sourcing current on the Ra CC line	CC pin voltage 0 V ≤ V_CCn ≤ 1.5 V	64	80	96	µA
CC1/CC2 CONNECT MANAGEMENT: UFP MODE (TPS25830-Q1)
I_{SRC_CCn}	Sourcing current	V_CTRL1 = V_CC and V_CTRL2 = V_CC, CC pin voltage: 0 V ≤ V_CCn ≤ 1.5 V (with CDP mode)	308	330	354	µA
I_{SRC_CCn}	Sourcing current	V_CTRL1 = V_CC and V_CTRL2 = GND, CC pin voltage: 0 V ≤ V_CCn ≤ 1.5 V (with SDP mode)	168	180	192	µA
CC1/CC2 CONNECT MANAGEMENT: UFP MODE (TPS25831-Q1)
I_{SRC_CCn}	Sourcing current	V_CTRL1 = V_CC and V_CTRL2 = V_CC, CC pin voltage: 0 V ≤ V_CCn ≤ 1.5 V (with CDP mode)	308	330	354	µA
I_{SRC_CCn}	Sourcing current	V_CTRL1 = V_CC and V_CTRL2 = GND, CC pin voltage: 0 V ≤ V_CCn ≤ 1.5 V (with SDP mode)	168	180	192	µA
I_{SRC_CCn}	Sourcing current	V_CTRL1 = GND and V_CTRL2 = V_CC, CC pin voltage: 0 V ≤ V_CCn ≤ 1.5 V (with DCP auto mode)	308	330	354	µA
I_REV	Reverse leakage current	CCx is the CC pin under test, CCy is the other CC pin. CC pin voltage VCCx = 5.5 V, CCy = 0V or floating, V_EN = 0 V, I_REV is current into CCx pin		0	5	µA
I_REV	Reverse leakage current	CCx is the CC pin under test, CCy is the other CC pin. CC pin voltage VCCx = 5.5 V, CCy = 0, V_EN = V_IN, I_REV is current into CCx pin under test		6	10	µA
FAULT, LD_DET, POL
V_OL	FAULT Output low voltage	I_{SNK_PIN} = 0.5 mA			250	mV
I_OFF	FAULT Off-state leakage	V_PIN = 5.5 V			1	µA
V_OL	LD_DET, POL Output low voltage	I_{SNK_PIN} = 0.5 mA			250	mV
I_OFF	LD_DET, POL Off-state leakage	V_PIN = 5.5 V			1	µA
THERM_WARN (TPS25831-Q1)
V_OL	THERM_WARN Output low voltage	I_{SNK_PIN} = 0.5 mA			250	mV
I_OFF	THERM_WARN Off-state leakage	V_PIN = 5.5 V			1	µA
CTRL1, CTRL2 - LOGIC INPUTS
V_IH	Rising threshold voltage			1.48	2	V
V_IL	Falling threshold voltage		0.85	1.30		V
V_HYS	Hysteresis			180		mV
I_IN	Input current		–1		1	µA
DP_IN AND DM_IN OVERVOLTAGE PROTECTION
V_{Dx_IN_OV}	Rising threshold for Dx_IN overvoltage protection	DP_IN or DM_IN rising	3.7	3.9	4.15	V
	Hysteresis			100		mV
R_{Dx_IN_DCHG_18V}	Discharge resistance for Dx_IN	VDx_IN = 18V, measure leakage current		94		kΩ
R_{Dx_IN_DCHG_5V}	Discharge resistance for Dx_IN	VDx_IN = 5V, measure leakage current		416		kΩ
HIGH-BANDWIDTH ANALOG SWITCH (TPS25830-Q1)
R_{DS_ON}	DP and DM switch on-resistance	V_{DP_OUT} = V_{DM_OUT} = 0 V, I_{DP_IN} = I_{DM_IN} = 30 mA		3.4	6.3	Ω
R_{DS_ON}	DP and DM switch on-resistance	V_{DP_OUT} = V_{DM_OUT} = 2.4 V, I_{DP_IN} = I_{DM_IN} = –15 mA		4.3	7.7	Ω
\|ΔR_{DS_ON}\|	Switch resistance mismatch between DP and DM channels	V_{DP_OUT} = V_{DM_OUT} = 0 V, I_{DP_IN} = I_{DM_IN} = 30 mA		0.05	0.15	Ω
\|ΔR_{DS_ON}\|	Switch resistance mismatch between DP and DM channels	V_{DP_OUT} = V_{DM_OUT} = 2.4 V, I_{DP_IN} = I_{DM_IN} = –15 mA		0.05	0.15	Ω
C_{IO_OFF}	DP/DM switch off-state capacitance	V_EN = 0 V, V_{DP_IN} = V_{DM_IN} = 0.3 V, Vac = 0.03 V_PP , f = 1 MHz		6.7		pF
C_{IO_ON}	DP/DM switch on-state capacitance	V_{DP_IN} = V_{DM_IN} = 0.3 V, Vac = 0.03 V_PP, f = 1 MHz		10		pF
O_IRR	Off-state isolation	V_EN = 0 V, f = 250 MHz		9		dB
X_TALK	On-state cross-channel isolation	f = 250 MHz		29		dB
I_lkg(OFF)	Off-state leakage current, DP_OUT and DM_OUT	V_EN = 0 V, V_{DP_IN} = V_{DM_IN} = 3.6 V, V_{DP_OUT} = V_{DM_OUT} = 0 V, measure I_{DP_OUT}and I_{DM_OUT}		0.1	1.5	µA
BW	Bandwidth (–3 dB)	R_L = 50 Ω		800		MHz
CHARGING DOWNSTREAM PORT (CDP) DETECT
V_{DM_SRC}	DM_IN CDP output voltage	V_{DP_IN} = 0.6 V, –250 µA < I_{DM_IN} < 0 µA	0.5	0.6	0.7	V
V_{DAT_REF}	DP_IN rising lower window threshold for V_{DM_SRC} activation		0.36	0.38	0.4	V
V_{DAT_REF}	Hysteresis			50		mV
V_{LGC_SRC}	DP_IN rising upper window threshold for VDM_SRC deactivation		0.8	0.84	0.88	V
V_{LGC_SRC_HYS}	Hysteresis			100		mV
I_{DP_SINK}	DP_IN sink current	V_{DP_IN} = 0.6 V	40	70	100	µA
BC 1.2 DOWNSTREAM CHARGING PORT (TPS25831-Q1)
R_{DPM_SHORT}	DP_IN and DM_IN shorting resistance			135	200	Ω
DIVIDER3 MODE (TPS25831-Q1)
V_{DP_DIV3}	DP_IN output voltage		2.57	2.7	2.84	V
V_{DM_DIV3}	DM_IN output voltage		2.57	2.7	2.84	V
R_{DP_DIV3}	DP_IN output impedance	I_{DP_IN} = –5 µA	24	30	36	kΩ
R_{DM_DIV3}	DM_IN output impedance	I_{DM_IN} = –5 µA	24	30	36	kΩ
1.2-V MODE (TPS25831-Q1)
V_{DP_1.2V}	DP_IN output voltage		1.12	1.2	1.26	V
V_{DM_1.2V}	DM_IN output voltage		1.12	1.2	1.26	V
R_{DP_1.2V}	DP_IN output impedance	I_{DP_IN} = –5 µA	84	100	126	kΩ
R_{DM_1.2V}	DM_IN output impedance	I_{DM_IN} = –5 µA	84	100	126	kΩ
RT/SYNC THRESHOLD (RT/SYNC PIN)
V_{IH_RT/SYNC}	RT/SYNC high threshold for external clock synchronization	Amplitude of SYNC clock AC signal (measured at SYNC pin)	3.5			V
V_{IL_RT/SYNC}	RT/SYNC low threshold for external clock synchronization	Amplitude of SYNC clock AC signal (measured at SYNC pin)			0.8	V
NTC TEMPERATURE SENSING (TPS25831-Q1)
V_{WARN_HIGH}	Temperature warning threshold rising		V_CC × 0.475	V_CC × 0.5	V_CC × 0.525	V
V_{WARN_HYS}	Hysteresis			V_CC x 0.1		V
V_{SD_HIGH}	Temperature shutdown threshold rising		V_CC × 0.618	V_CC × 0.65	V_CC × 0.683	V
V_{SD_HYS}	Hysteresis			V_CC x 0.1		V
THERMAL SHUTDOWN
T_SD	Thermal shutdown	Shutdown threshold		160		°C
T_SD	Thermal shutdown	Recovery threshold		140		°C