JAJSHI6G June 2018 – July 2021 TPS25830-Q1 , TPS25831-Q1
PRODUCTION DATA
NAME | 830-Q1 NO. |
831-Q1 NO. |
TYPE (1) | I/O | DESCRIPTION |
---|---|---|---|---|---|
AGND | 16 | 16 | G | – | Analog ground terminal. Ground reference for internal references and logic. All electrical parameters are measured with respect to this pin. Connect to system ground on PCB. |
BOOT | 32 | 32 | P | Boot-strap capacitor connection for HS FET driver. Connect a high quality 100-nF capacitor from this pin to the SW pin. | |
BUS | 15 | 15 | A | I | VBUS discharge input. Connect to VBUS on USB Connector. |
CC1 | 20 | 20 | A | I/O | Analog input and output. Connect to Type-C CC1 pin. |
CC2 | 19 | 19 | A | I/O | Analog input and output. Connect to Type-C CC2 pin. |
CSN/OUT | 13 | 13 | A | I | Negative input of current sense amplifier, also buck output for internal voltage regulation. |
CSP | 14 | 14 | A | I | Positive input of current sense amplifier. |
CTRL1 | 5 | 5 | A | I | Logic-level control inputs for device/system configuration (see Truth Table). |
CTRL2 | 6 | 6 | A | I | Logic-level control inputs for device/system configuration (see Truth Table). |
DM_IN | 17 | 17 | A | DM data line. Connect to USB connector. | |
DM_OUT | 8 | – | A | DM data line. Connect to USB host controller. | |
DP_IN | 18 | 18 | A | DP data line. Connect to USB connector. | |
DP_OUT | 7 | – | A | DP data line. Connect to USB host controller. | |
EN/UVLO | 4 | 4 | A | Enable pin. Do not float. High = on, Low = off. Can be tied to VIN. Precision enable input allows adjustable UVLO by external resistor divider. | |
FAULT | 24 | 24 | A | O | Active LOW open-drain output. Asserted during fault conditions (see Table 10-4). |
ILIMIT | 12 | 12 | A | External resistor used to set the current-limit threshold (see Table 10-2). | |
IMON | 11 | 11 | A | External resistor used to set the max cable comp voltage at full load current. | |
IN | 1, 2, 3 | 1, 2, 3 | P | I | Input Supply to regulator. Connect a high-quality bypass capacitor(s) directly to this pin and PGND. |
LD_DET | 23 | 23 | A | O | Active LOW open-drain output. Asserted when a Type-C UFP is identified on the CC lines. |
LS_GD | 10 | 10 | A | External NMOS gate driver. For TPS25830-Q1, LS_GD pin must be pulled up through a 2.2-kΩ resistor under average current limit mode (see Current Limit Setting using RILIMIT). | |
NTC | – | 8 | I | Input for negative temperature coefficient resistor divider. Use to monitor external PCB temperature (see Thermal Sensing with NTC (TPS25831-Q1)). | |
PGND | 25, 26, 27 | 25, 26, 27 | G | – | Power ground terminal. Connect to system ground and AGND. Connect to bypass capacitor with short wide traces. |
POL | 22 | 22 | A | O | Active LOW open-drain output. Signals which Type-C CC pin is connected to the CC line. This gives cable orientation information needed to mux the super speed lines. Asserted when the CC2 pin is connected to the CC line in the cable. |
RT/SYNC | 9 | 9 | A | Resistor Timing or External Clock input. An internal amplifier holds this terminal at a fixed voltage when using an external resistor to ground to set the switching frequency. If the terminal is pulled above the PLL upper threshold, a mode change occurs and the terminal becomes a synchronization input. The internal amplifier is disabled and the terminal is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming. | |
SW | 28, 29, 30, 31 | 28, 29, 30, 31 | P | Switching output of the regulator. Internally connected to source of the HS FET and drain of the LS FET. Connect to power inductor. | |
THERM_WARN | – | 7 | A | O | Active LOW open-drain output. Asserted when voltage at the NTC pin increases above the thermal warning threshold. |
VCC | 21 | 21 | P | Output of internal bias supply. Used as supply to internal control circuits. Connect a high quality 2.2-µF capacitor from this pin to GND. |