JAJSHY1E September   2019  – March 2022 TPS25840-Q1 , TPS25842-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Buck Regulator
      2. 10.3.2  Enable/UVLO
      3. 10.3.3  Switching Frequency and Synchronization (RT/SYNC)
      4. 10.3.4  Spread-Spectrum Operation
      5. 10.3.5  VCC, VCC_UVLO
      6. 10.3.6  Minimum ON-time, Minimum OFF-time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Bootstrap Voltage (BOOT)
      9. 10.3.9  RSNS, RSET, RILIMIT and RIMON
      10. 10.3.10 Overcurrent and Short Circuit Protection
        1. 10.3.10.1 Current Limit Setting using RILIMIT
        2. 10.3.10.2 Buck Average Current Limit Design Example
        3. 10.3.10.3 External MOSFET Gate Drivers
        4. 10.3.10.4 Cycle-by-Cycle Buck Current Limit
      11. 10.3.11 Overvoltage, IEC and Short-to-Battery Protection
        1. 10.3.11.1 V BUS and V CSN/OUT Overvoltage Protection
        2. 10.3.11.2 DP_IN and DM_IN Protection
      12. 10.3.12 Cable Compensation
        1. 10.3.12.1 Cable Compensation Design Example
      13. 10.3.13 USB Port Control
      14. 10.3.14 FAULT Response
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 Device Power Pins (IN, CSN/OUT, and PGND)
      17. 10.3.17 Thermal Shutdown
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
      3. 10.4.3 Device Truth Table (TT)
      4. 10.4.4 USB Port Operating Modes
        1. 10.4.4.1 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
        2. 10.4.4.2 Charging Downstream Port (CDP) Mode
        3. 10.4.4.3 Client Mode
      5. 10.4.5 High-bandwidth Data-line Switches
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1  Output Voltage
        2. 11.2.2.2  Switching Frequency
        3. 11.2.2.3  Inductor Selection
        4. 11.2.2.4  Output Capacitor Selection
        5. 11.2.2.5  Input Capacitor Selection
        6. 11.2.2.6  Bootstrap Capacitor Selection
        7. 11.2.2.7  VCC Capacitor Selection
        8. 11.2.2.8  Enable and Under Voltage Lockout Set-Point
        9. 11.2.2.9  Current Limit Set-Point
        10. 11.2.2.10 Cable Compensation Set-Point
        11. 11.2.2.11 FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Ground Plane and Thermal Considerations
    3. 13.3 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Related Links
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 サポート・リソース
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.8 Typical Characteristics

Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF, COUT_CSN = 0.1 µF, CBUS = 1 µF, TA = 25 °C.

GUID-BDE4A2C3-8488-4916-8391-10C6AF019AEF-low.gif
VCSN = 8 VINT = 5.1 kΩ
Figure 8-1 Non-Switching Quiescent Current
GUID-89BDC598-BC6F-4E03-B093-86680119956F-low.gif
Figure 8-3 Precision Enable Threshold
GUID-4BCD9227-15A0-4716-9F86-E1302156E7DB-low.gif
A.
Figure 8-5 VCC vs Input Voltage
GUID-AF80A2BE-9B93-44FD-865A-3249A4D235BA-low.gif
Figure 8-7 High-side Current Limit vs Input Voltage
GUID-7427DAE3-1596-4543-BA44-EC896EB2F7DF-low.gif
Figure 8-9 Low-side MOSFET on Resistance vs Junction Temperature
GUID-9A8AAA37-39B9-474D-A26A-62129BD5AFC1-low.gif
RT = 8.87 kΩ
Figure 8-11 Switching Frequency vs VIN Voltage
GUID-3A10A24A-DB90-427C-BF37-E29C29877B56-low.gif
RSNS = 15 mΩ RSET = 300 Ω
Figure 8-13 External FET Current Limit vs Junction Temperature
GUID-DEC46EFE-BCB9-41E4-B698-6BFAE5CBDA66-low.gif
VCSN/OUT = 5.1 V RIMON = 0 kΩ
Figure 8-15 LS_GD Gate Voltage vs Junction Temperature
GUID-8E3733B6-E3F1-4366-9C8E-314C57B6FFAE-low.gif
RSNS = 15 mΩ RSET = 300 Ω RIMON = 13 kΩ
Figure 8-17 Cable Compensation Voltage vs Load Current
GUID-F51FD466-9E5F-4CB8-B5C4-71D52191C121-low.gif
Figure 8-19 DP_IN Overvoltage Protection Threshold vs Junction Temperature
GUID-F663109A-F630-403B-B0DA-3933E4FED8E2-low.gif
Measured source with 10-cm cable
Figure 8-21 Bypassing the TPS2584x-Q1 Data Switch
GUID-783821CB-F63A-4998-844E-D7949925866C-low.gif
A.
Figure 8-23 Data Transmission Characteristics vs Frequency
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A.
Figure 8-25 On-state Cross-channel Isolation vs Frequency
GUID-7ABAAB0D-9407-4C8C-9D9D-B4F14C2A85BE-low.gif
EN = 0 V
Figure 8-2 Shutdown Quiescent Current
GUID-A303D1A0-F964-484E-B3B0-985D7FE74E26-low.gif
Figure 8-4 VIN UVLO Threshold
GUID-AAC28185-61DB-4E12-BCF3-341BEC761299-low.gif
RIMON = 0 Ω
Figure 8-6 VCSN/OUT Voltage vs Junction Temperature
GUID-51FCB56B-E953-4FF7-8DAE-45EC43EC54F2-low.gif
Figure 8-8 High-side MOSFET on Resistance vs Junction Temperature
GUID-115D42DB-B528-431A-AE55-F88CA8BAF3DC-low.gif
RT = 49.9 kΩ
Figure 8-10 Switching Frequency vs Junction Temperature
GUID-ED7815AC-9F55-49EA-A49A-1CAB6C36C2C8-low.gif
RSNS = 15 mΩ RSET = 300 Ω
Figure 8-12 Buck Average Current Limit vs Junction Temperature
GUID-73A73584-1323-4B1A-95A0-6C0D5FA3E5FE-low.gif
A.
Figure 8-14 LS_GD Gate Source Current vs Junction Temperature
GUID-A45BF75C-044F-4472-89D1-61FE1985689F-low.gif
RSNS = 15 mΩ RSET = 300 Ω RIMON = 13 kΩ
Figure 8-16 Cable Compensation Voltage vs Junction Temperature
GUID-871A04E5-C052-4600-9742-B61F2FFA0065-low.gif
Figure 8-18 VBUS Overvoltage Protection Threshold vs Junction Temperature
GUID-7F8F876A-F782-44BD-921C-AA3F56D6A42C-low.gif
Figure 8-20 DM_IN Overvoltage Protection Threshold vs Junction Temperature
GUID-E62E3A13-0B2F-4358-9246-68D37D03E950-low.gif
Measured on TPS25830-Q1 EVM with 10-cm cable
Figure 8-22 Through the TPS2584x-Q1 Data Switch
GUID-7B0732A4-90A7-48BA-BA73-15D39A8E2105-low.gif
A.
Figure 8-24 Off-state Data-Switch Isolation vs Frequency