Layout is a critical portion of good power supply
design. The following guidelines help users design a PCB with the best power
conversion performance, thermal performance, and minimized generation of unwanted
EMI. For more detailed EMC design consideration and test report, please see the
PCB
Layout and Parameters Recommendation for TPS2583X EMC Performance
application report.
- Input capacitor: The input bypass capacitor, CIN, must be
placed as close as possible to the IN and PGND
pins. Grounding for both the input and output
capacitors must consist of localized top side
planes that connect to the PGND pin and PAD. A
combination of different values and packages of
capacitors can help improve the EMC performance
(for example: 10 μF + 0.1 μF + 2.2 nF). Besides,
the distance between the input filter section and
the output power section must be at least 15mm to
prevent the output high-frequency signal from
coupling into the input filter. A 10-µF cap cross
VIN and PGND pin on top of SW is
suggested for TPS2584x-Q1.
- VCC bypass capacitor: Place bypass capacitors for VCC close to the VCC pin and ground the bypass capacitor to device ground.
- Use a ground plane in one of the middle layers as noise shielding and heat dissipation path.
- Connect the thermal pad to the ground plane. The QFN package has a thermal pad (PAD) connection that must be soldered down to the PCB ground plane. This pad acts as a heat-sink connection. The integrity of this solder connection has a direct bearing on the total effective RθJA of the application.
- Make VIN, VOUT and ground bus connections as wide as possible.
This action reduces any voltage drops on the input or output
paths of the converter and maximizes efficiency.
- Provide enough PCB area for proper heat sinking. As stated in the section, enough
copper area must be used to ensure a low
RθJA, commensurate with the maximum
load current and ambient temperature. Make the top
and bottom PCB layers with 2-ounce copper and no
less than one ounce. Use an array of heat-sinking
vias to connect the thermal pad (PAD) to the
ground plane on the bottom PCB layer. If the PCB
design uses multiple copper layers (recommended),
thermal vias can also be connected to the inner
layer heat-spreading ground planes.
- The SW pin connecting to the inductor must be as short as possible, and just
wide enough to carry the load current without excessive heating. Short, thick traces or
copper pours (shapes) bring a high current conduction capacity to minimize parasitic
resistance, but also cause a larger parasitic capacitance. Thus a balance must be found
between smaller parasitic resistance and larger parasitic capacitance. And the current
path must be kept straight forward to the inductor, otherwise the L-shaped or T-shaped
path makes a sudden change of the impedance which causes signal reflection and impacts the
performance of EMC. The output capacitors must be placed close to the VOUT end
of the inductor and closely grounded to PGND pin and exposed PAD. Besides, do not punch
vias on SW lines. Using shielded inductors or molded inductors to reduce high-frequency
radiation.
- Sense and Set Resistors: The RSNS and RSET
resistors connect to the current sense amplifier inputs at the CSP and CSN/OUT pins. For
best current limit and cable compensation accuracy; short, parallel traces give the best
performance. If it is not possible to place RSNS and RSET near the
CSP and CSN/OUT pins, TI recommends that the traces from sense resistor be routed in
parallel and of similar lengths. A small filter capacitor in parallel with RSNS
and a small filter capacitor from CSN/OUT to AGND help decouple noise.
- RILIMIT and RIMON resistors must be placed as close as possible to the ILIMIT and IMON pins and connected to AGND. If needed, these components can be placed on the bottom side of the PCB with signals routed through small vias.
- Trace routing of DP_IN, DM_IN, DP_OUT, and DM_OUT: Route these traces as micro-strips with nominal differential impedance of 90 Ω. Minimize the use of vias in the high-speed data lines. Keep the reference GND plane devoid from cuts or splits above the differential pairs to prevent impedance discontinuities.
- FAULT are open-drain outputs. They can be connected to the VCC pin via pull-up resistors. Suggested resistor value is 100 kΩ.
- The area enclosed by current loop of input side and output side must be as small as possible; the area enclosed by the BOOT circuit must be as small as possible.
- Power ground PGND and the signal ground AGND must be separated in the actual PCB layout.