JAJSHY1E September   2019  – March 2022 TPS25840-Q1 , TPS25842-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Buck Regulator
      2. 10.3.2  Enable/UVLO
      3. 10.3.3  Switching Frequency and Synchronization (RT/SYNC)
      4. 10.3.4  Spread-Spectrum Operation
      5. 10.3.5  VCC, VCC_UVLO
      6. 10.3.6  Minimum ON-time, Minimum OFF-time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Bootstrap Voltage (BOOT)
      9. 10.3.9  RSNS, RSET, RILIMIT and RIMON
      10. 10.3.10 Overcurrent and Short Circuit Protection
        1. 10.3.10.1 Current Limit Setting using RILIMIT
        2. 10.3.10.2 Buck Average Current Limit Design Example
        3. 10.3.10.3 External MOSFET Gate Drivers
        4. 10.3.10.4 Cycle-by-Cycle Buck Current Limit
      11. 10.3.11 Overvoltage, IEC and Short-to-Battery Protection
        1. 10.3.11.1 V BUS and V CSN/OUT Overvoltage Protection
        2. 10.3.11.2 DP_IN and DM_IN Protection
      12. 10.3.12 Cable Compensation
        1. 10.3.12.1 Cable Compensation Design Example
      13. 10.3.13 USB Port Control
      14. 10.3.14 FAULT Response
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 Device Power Pins (IN, CSN/OUT, and PGND)
      17. 10.3.17 Thermal Shutdown
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
      3. 10.4.3 Device Truth Table (TT)
      4. 10.4.4 USB Port Operating Modes
        1. 10.4.4.1 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
        2. 10.4.4.2 Charging Downstream Port (CDP) Mode
        3. 10.4.4.3 Client Mode
      5. 10.4.5 High-bandwidth Data-line Switches
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1  Output Voltage
        2. 11.2.2.2  Switching Frequency
        3. 11.2.2.3  Inductor Selection
        4. 11.2.2.4  Output Capacitor Selection
        5. 11.2.2.5  Input Capacitor Selection
        6. 11.2.2.6  Bootstrap Capacitor Selection
        7. 11.2.2.7  VCC Capacitor Selection
        8. 11.2.2.8  Enable and Under Voltage Lockout Set-Point
        9. 11.2.2.9  Current Limit Set-Point
        10. 11.2.2.10 Cable Compensation Set-Point
        11. 11.2.2.11 FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Ground Plane and Thermal Considerations
    3. 13.3 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Related Links
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 サポート・リソース
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.2.1 Design Requirements

To begin the design process, a few parameters must be known:

  • Cable compensation: Total resistance including cable resistance, contact resistance of connectors, TPS2584x-Q1 current sense resistor and external NFET rDS(on) (if used). Refer to Figure 10-19 for examples of resistance in an automotive application.
  • The maximum continuous output current for the charging port. The minimum current-limit setting of TPS2584x-Q1 device must be higher than this current.

For this example, use the parameters listed in Table 11-1 as the input parameters.

Table 11-1 Design Example Parameters
PARAMETERVALUE
Input Voltage, VIN13.5-V typical, range from 6 V to 18 V
Output Voltage, VOUT5.1 V
Maximum Output Current IOUT(MAX)3.0 A
Transient Response 0.3 A to 3 A5%
Output Voltage Ripple50 mV
Input Voltage Ripple400 mV
Switching Frequency fSW400 kHz
Cable Resistance for Cable Compensation300 mΩ
Current Limit by Buck Average3.3 A
Table 11-2 L, and COUT Typical Values
fSWVOUT without Cable CompensationCIN + CHFLCurrent LimitCCSPCCSN/OUTCBUS
400 kHz5.10 V1 × 10 µF + 1 × 100 nF10 µHBuck Avg5 × 22 µF100 nF1 to 4.7 µF
400 kHz5.10 V1 × 10 µF + 1 × 100 nF10 µHExt. NFET5 × 22 µF100 nF1 to 4.7 µF
2100 kHz5.10 V1 × 10 µF + 1 × 100 nF2.2 µHBuck Avg2 × 22 µF100 nF1 to 4.7 µF
  1. Inductance value is calculated based on VIN = 18 V.
  2. All the COUT values are after derating.