When load draws current during the turn-on sequence, there is additional power dissipated. Considering a resistive load R_L(SU) during start-up, load current ramps up proportionally with increase in output voltage during t_dVdT time. Typical ramp-up of output voltage, Load current and power dissipation in the device is shown in Figure 10-4 and power dissipation with respect to time is plotted in Figure 10-5. The additional power dissipation during start-up phase is calculated as shown in Equation 17 and Equation 18.

Equation 17.

Equation 18.

Where R_L(SU) is the load resistance present during start-up. Average energy loss in the internal FET during charging time due to resistive load is given by Equation 19.

Equation 19.

V(IN) = 12 V

C(dVdT) = 1 nF

RL(SU) = 4.8 Ω

Figure 10-4 Start-Up With Load

V(IN) = 12 V

C(dVdT) = 1 nF

RL(SU) = 4.8 Ω

Figure 10-5 P_D(LOAD) in Load During Start-Up

On solving Equation 19 the average power loss in the internal FET due to load is shown in Equation 20.

Equation 20.

Total power dissipated in the device during startup is shown is Equation 21.

Equation 21.

Total current during startup is given by Equation 22.

Equation 22.

If I_(STARTUP) > I_(LIM), the device limits the current to I_(LIM) and the current limited charging time is determined by Equation 23.

Equation 23.

The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as shown in Figure 10-6.

Taken on 2-Layer board, 2oz.(0.08-mm thick) with GND plane area: 14 cm² (Top) and 20 cm² (bottom)

Figure 10-6 Thermal Shutdown Limit Plot

For the design example under discussion,

Select ramp-up capacitor C_(dVdT) = 1nF, using Equation 24.

Equation 24.

The inrush current drawn by the load capacitance (C_(OUT)) during ramp-up using Equation 25.

Equation 25.

The inrush Power dissipation is calculated, using Equation 26.

Equation 26.

For 7.2 W of power loss, the thermal shut down time of the device must not be less than the ramp-up time t_dVdT to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 10-6 at T_A = 85°C, for 7.2 W of power the shutdown time is approximately 60 ms. So it is safe to use 1 ms as start-up time without any load on output.

Considering the start-up with load 4.8 Ω, the additional power dissipation, when load is present during start up is calculated, using Equation 27.

Equation 27.

The total device power dissipation during start up is given by Equation 28.

Equation 28.

From thermal shutdown limit graph at T_A = 85°C, the thermal shutdown time for 12.2 W is close to 7.5 ms. It is safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and input voltage. So it is well within acceptable limits to use the 1 nF capacitor with start-up load of 4.8 Ω.

If there is a need to decrease the power loss during start-up, it can be done with increase of C_(dVdT) capacitor.

To illustrate, choose C_(dVdT) = 1.5 nF as an option and recalculate:

Equation 29.

Equation 30.

Equation 31.

Equation 32.

Equation 33.

From thermal shutdown limit graph at T_A = 85°C, the shutdown time for 10-W power dissipation is approximately 17 ms, which increases the margins further for shutdown time and ensures successful operation during start up and steady state conditions.

The spreadsheet tool available on the web can be used for iterative calculations.