JAJSOA2 December   2022 TPS25961

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 代表的特性
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 過電圧保護 (UVP) および低電圧ロックアウト (UVLO)
      2. 7.3.2 Overvoltage Protection
      3. 7.3.3 Inrush Current, Overcurrent and Short Circuit Protection
        1. 7.3.3.1 Slew Rate and Inrush Current Control (dVdt)
        2. 7.3.3.2 Active Current Limiting
        3. 7.3.3.3 Short-Circuit Protection
      4. 7.3.4 Overtemperature Protection (OTP)
      5. 7.3.5 Fault Response
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 代表的なアプリケーション
      1. 8.2.1 Adapter input protection for set-top boxes
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Programming the Current-Limit Threshold: RILM Selection
        2. 8.2.3.2 低電圧および過電圧ロックアウトの設定点
        3. 8.2.3.3 Output Voltage Rise Time (tR)
      4. 8.2.4 Application Curves
    3. 8.3 Application Example
      1. 8.3.1 Application Curves
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 過渡保護
      2. 8.4.2 Output Short-Circuit Measurements
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 商標
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.5 Fault Response

Table 7-3 summarizes the protection response to various fault conditions.

Table 7-3 Fault Response
Event / FaultProtection ResponseFault Latched Internally

Steady-state

N/A

N/A

OvertemperatureShutdownYes
UndervoltageCut-offNo
OvervoltageCut-offNo
OvercurrentCurrent LimitNo
Short-circuitCurrent LimitNo

Once the device turns off due to a latched fault, power cycling the part or pulling the EN/UVLO pin voltage below VSD(F) clears the fault. Pulling the EN/UVLO just below the UVLO threshold has no impact on the device in this condition.

At the end of the tTSD,RST timer after a latched fault, the device will attempt to automatically restart 3 times. If the fault was caused by a transient condition which goes away and the device is able to recover and reach steady state, it clears the fault counter.

If the fault is persistent, the device will eventually shut down completely after 3 attempts and then remain latched-off till it's power cycled.