JAJSMF6C november   2021  – april 2023 TPS2597

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO and UVP)
      2. 8.3.2 Overvoltage Lockout (OVLO)
      3. 8.3.3 Overvoltage Clamp (OVC)
      4. 8.3.4 Inrush Current, Overcurrent, and Short Circuit Protection
        1. 8.3.4.1 Slew Rate (dVdt) and Inrush Current Control
        2. 8.3.4.2 Circuit-Breaker
        3. 8.3.4.3 Active Current Limiting
        4. 8.3.4.4 Short-Circuit Protection
      5. 8.3.5 Analog Load Current Monitor
      6. 8.3.6 Overtemperature Protection (OTP)
      7. 8.3.7 Fault Response and Indication (FLT)
      8. 8.3.8 Power-Good Indication (PG)
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Single Device, Self-Controlled
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
        2. 9.2.2.2 Setting Undervoltage and Overvoltage Thresholds
        3. 9.2.2.3 Setting Output Voltage Rise Time (tR)
        4. 9.2.2.4 Setting Power-Good Assertion Threshold
        5. 9.2.2.5 Setting Overcurrent Threshold (ILIM)
        6. 9.2.2.6 Setting Overcurrent Blanking Interval (tITIMER)
      3. 9.2.3 Application Curves
    3. 9.3 Parallel Operation
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 Output Short-Circuit Measurements
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Fault Response and Indication (FLT)

Table 8-3 summarizes the device response to various fault conditions. Additionally, an active low external fault indication (FLT) pin is available on the TPS25970x variants.

Table 8-3 Fault Summary

EVENT

PROTECTION RESPONSE

FAULT LATCHED INTERNALLY

FLT PIN STATUS (1)FLT ASSERTION DELAY(1)

Overtemperature

Shutdown

Y

L

Undervoltage (UVP or UVLO)

Shutdown

N

H

Input Overvoltage

Shutdown(1)(2)

N

H

Voltage Clamp(2)

N

N/A

Transient Overcurrent (ILIM < IOUT < 2 × ILIM)

None

N

N

Persistent Overcurrent

Circuit Breaker(3)

Y

N/A

Persistent OvercurrentCurrent Limit(4)

N

L

tITIMER

Output Short-Circuit to GND

Circuit Breaker followed by Current Limit

N

H

ILM Pin Open

(During Steady State)

Shutdown

N

L

tITIMER

ILM Pin Shorted to GND

Shutdown

Y

L

tITIMER

Applicable to TPS25970x variants only.
Applicable to TPS25972x variants only.
Applicable to TPS25974x variants only.
Applicable to TPS25970x and TPS25972x variants only.

Faults which are latched internally can be cleared either by power cycling the part (pulling VIN to 0 V) or by pulling the EN/UVLO pin voltage below VSD. This action also releases the FLT pin for the TPS25970x variants and resets the tRSTtimer for the TPS2597xA (auto-retry) variants.

During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device. This fact is true for both TPS2597xL (latch-off) and TPS2597xA (auto-retry) variants.

For TPS2597xA (auto-retry) variants, on expiry of the tRSTtimer after a fault, the device restarts automatically and the FLT pin is de-asserted (TPS25970A variant).