JAJSMF7B april   2022  – june 2023 TPS25981

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
      1.      16
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO and UVP)
      2. 8.3.2 Overvoltage Lockout (OVLO)
      3. 8.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.3.1 Slew Rate (dVdt) and Inrush Current Control
        2. 8.3.3.2 Circuit-Breaker During Steady-State
        3. 8.3.3.3 Active Current Limiting During Start-Up
        4. 8.3.3.4 Short-Circuit Protection
      4. 8.3.4 Analog Load Current Monitor
      5. 8.3.5 Overtemperature Protection (OTP)
      6. 8.3.6 Fault Response and Indication (FLT)
      7. 8.3.7 Power Good Indication (PG)
      8. 8.3.8 Quick Output Discharge (QOD)
      9. 8.3.9 Reverse Current Blocking FET Driver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Single Device, Self-Controlled
      2. 9.1.2 Parallel Operation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
        2. 9.2.2.2 Setting Output Voltage Rise Time (tR)
        3. 9.2.2.3 Setting Overcurrent Threshold (ILIM)
        4. 9.2.2.4 Setting Overcurrent Blanking Interval (tITIMER)
        5. 9.2.2.5 Voltage Drop
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.6 Fault Response and Indication (FLT)

The following table summarizes the device response to various fault conditions. Additionally, an active low external fault indication (FLT) pin is available.

Table 8-2 Fault Summary

Event

Protection Response

Fault Latched Internally

FLT Pin StatusFLT Assertion Delay

Overtemperature

Shutdown

Y

L

Undervoltage (UVP or UVLO)

Shutdown

N

H

Input overvoltage

Shutdown

N

H

Transient overcurrent (ILIM < IOUT < 2 × ILIM)

None

N

N

Persistent overcurrent

Circuit-breaker

Y

N/A

Output short circuit to GND

Circuit-breaker followed by current limit

N

H

ILM pin open

(during steady-state)

Shutdown

N

L

tITIMER

ILM pin shorted to GND

Shutdown

Y

L

tITIMER

Faults which are latched internally can be cleared either by power cycling the part (pulling VIN to 0 V) or by pulling the EN/UVLO pin voltage below VSD. This action also releases the FLT pin and resets the tRSTtimer for the TPS25981xA (auto-retry) variants.

During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device. This fact is true for both TPS25981xL (latch-off) and TPS25981xA (auto-retry) variants.

For TPS25981xA (auto-retry) variants, on expiry of the tRSTtimer after a fault, the device restarts automatically and the FLT pin is de-asserted.