JAJSQU2A August   2023  – October 2023 TPS25983

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Protection (UVLO and UVP)
      2. 8.3.2 Overvoltage Protection (OVP)
      3. 8.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.3.1 Slew Rate and Inrush Current Control (dVdt)
        2. 8.3.3.2 Circuit Breaker
        3. 8.3.3.3 Active Current Limiting
        4. 8.3.3.4 Short-Circuit Protection
      4. 8.3.4 Overtemperature Protection (OTP)
      5. 8.3.5 Analog Load Current Monitor (IMON)
      6. 8.3.6 Power Good (PG)
      7. 8.3.7 Reverse Current Blocking FET Driver
      8. 8.3.8 Fault Response
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Standby Power Rail Protection in Datacenter Servers
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
        2. 9.2.2.2 Setting the Current Limit Threshold: RILIM Selection
        3. 9.2.2.3 Setting the Undervoltage and Overvoltage Lockout Set Point
        4. 9.2.2.4 Choosing the Current Monitoring Resistor: RIMON
        5. 9.2.2.5 Setting the Output Voltage Ramp Time (TdVdt)
          1. 9.2.2.5.1 Case 1: Start-Up Without Load: Only Output Capacitance COUT Draws Current
          2. 9.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance COUT and Load Draw Current
        6. 9.2.2.6 Setting the Transient Overcurrent Blanking Interval (tITIMER)
        7. 9.2.2.7 Setting the Auto-Retry Delay and Number of Retries
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Optical Module Power Rail Path Protection
        1. 9.3.1.1 Design Requirements
        2. 9.3.1.2 Device Selection
        3. 9.3.1.3 External Component Settings
        4. 9.3.1.4 Voltage Drop
        5. 9.3.1.5 Application Curves
      2. 9.3.2 Input Protection for 12-V Rail Applications: PCIe Cards, Storage Interfaces, and DC Fans
      3. 9.3.3 Priority Power MUXing
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 Output Short-Circuit Measurements
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.8 Fault Response

The following events trigger an internal fault which causes the device to shut down:

  • Overtemperature protection
  • Circuit-breaker operation
  • ITIMER pin short to GND
  • ILIM pin short to GND
Once the device shuts down due to a fault, even if the associated external fault is subsequently cleared, the fault stays latched internally and the output cannot turn on again until the latch is reset. The fault latch can be externally reset by one of the following methods:
  • Input supply voltage is driven low (< VUVP(F))
  • EN/UVLO voltage is driven low (< VSD)
The fault latch can also be reset by an internal auto-retry logic. The user can either disable the auto-retry behavior completely (latch-off behavior) or configure the device to auto-retry indefinitely or for a limited number of times before latching off. The auto-retry behavior is controlled by the connections on the RETRY_DLY and NRETRY pins.

Table 8-3 Pin Configurable Fault Response
EN/UVLORETRY_DLYNRETRYDEVICE STATE
LXXDisabled
HShort to GNDXNo auto-retry (Latch-off)
HOpenOpenAuto-retry 4 times with minimum delay between retries and then latch-off
HOpenShort to GNDAuto-retry indefinitely with minimum delay between retries
HCapacitor to GNDCapacitor to GNDAuto-retry delay and count as per Equation 10 and Equation 11
HCapacitor to GNDOpenAuto-retry 4 times with finite delay between retries as per Equation 10 and then latch-off
HCapacitor to GNDShort to GNDAuto-retry indefinitely with finite delay between retries as per Equation 10

To configure the part for a finite number of auto-retries with a finite auto-retry delay, first choose the capacitor value on RETRY_DLY pin using the following equation.

Equation 10. GUID-4665381C-DEC7-4BEE-B8DD-47D36BD8A3BF-low.gif

Next, choose the capacitor value on the NRETRY pin using the following equation.

Equation 11. GUID-1B029672-68E8-4B43-90C5-4DA347027896-low.gif

The number of auto-retries is quantized to certain discrete levels as shown in Table 8-4.

Table 8-4 NRETRY Quantization Levels
NRETRY Calculated From Equation 11 NRETRY Actual
0 < N < 4 4
4 < N < 16 16
16 < N < 64 64
64 < N < 256 256
256 < N < 1024 1024
Table 8-5 NRETRY and RETRY_DLY Combination Examples
Auto Retry Delay915 ms416 ms91.7 ms9.3 ms3 ms
RETRY_DLY Capacitor22 nF10 nF2.2 nF220 pF68 pF
No. of Auto RetriesNRETRY Capacitor
4Open
1647 nF22 nF4.7 nF1 nF220 pF
640.22 μF0.1 μF22 nF2.2 nF1 nF
2561 μF0.47 μF0.1 μF10 nF4.7 nF
10243.3 μF1.5 μF0.47 μF33 nF10 nF
InfiniteShort to GND

A spreadsheet design tool TPS25983xx Design Calculator is also available for simplified calculations.

GUID-14941664-E13D-450E-82CB-124523243126-low.gifFigure 8-10 Auto-Retry After Fault

The auto-retry logic has a mechanism to reset the count to zero if two consecutive faults occur far apart in time. This mechanism makes sure that the auto-retry response to any later fault is handled as a fresh sequence and not as a continuation of the previous fault. If the fault which triggered the shutdown and subsequent auto-retry cycle is cleared eventually and does not occur again for a duration equal to 7 retry delay timer periods starting from the last fault, the auto-retry logic resets the internal auto-retry count to zero.