JAJSQU2A August   2023  – October 2023 TPS25983

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Protection (UVLO and UVP)
      2. 8.3.2 Overvoltage Protection (OVP)
      3. 8.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.3.1 Slew Rate and Inrush Current Control (dVdt)
        2. 8.3.3.2 Circuit Breaker
        3. 8.3.3.3 Active Current Limiting
        4. 8.3.3.4 Short-Circuit Protection
      4. 8.3.4 Overtemperature Protection (OTP)
      5. 8.3.5 Analog Load Current Monitor (IMON)
      6. 8.3.6 Power Good (PG)
      7. 8.3.7 Reverse Current Blocking FET Driver
      8. 8.3.8 Fault Response
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Standby Power Rail Protection in Datacenter Servers
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
        2. 9.2.2.2 Setting the Current Limit Threshold: RILIM Selection
        3. 9.2.2.3 Setting the Undervoltage and Overvoltage Lockout Set Point
        4. 9.2.2.4 Choosing the Current Monitoring Resistor: RIMON
        5. 9.2.2.5 Setting the Output Voltage Ramp Time (TdVdt)
          1. 9.2.2.5.1 Case 1: Start-Up Without Load: Only Output Capacitance COUT Draws Current
          2. 9.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance COUT and Load Draw Current
        6. 9.2.2.6 Setting the Transient Overcurrent Blanking Interval (tITIMER)
        7. 9.2.2.7 Setting the Auto-Retry Delay and Number of Retries
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Optical Module Power Rail Path Protection
        1. 9.3.1.1 Design Requirements
        2. 9.3.1.2 Device Selection
        3. 9.3.1.3 External Component Settings
        4. 9.3.1.4 Voltage Drop
        5. 9.3.1.5 Application Curves
      2. 9.3.2 Input Protection for 12-V Rail Applications: PCIe Cards, Storage Interfaces, and DC Fans
      3. 9.3.3 Priority Power MUXing
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 Output Short-Circuit Measurements
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.3.3 Active Current Limiting

The TPS25983xL (Current Limiter) variants respond to output overcurrent conditions by actively regulating the current to a set limit after a user adjustable fault blanking interval. During steady-state operation, if the load current exceeds a user adjustable overcurrent threshold (ILIM) set by the ILIM pin resistor (RILIM), but lower than the fast-trip threshold (IFT), the device starts discharging the ITIMER pin capacitor using an internal pull-down current (IITIMER). If the load current drops below the overcurrent threshold before the ITIMER capacitor voltage drops by ΔVITIMER, the current limit action is not engaged and the ITIMER is reset by pulling it up to VINT internally. This allows short transient overcurrent pulses to pass through the device without limiting the current. If the overcurrent condition persists, the ITIMER capacitor continues to discharge and once it falls by ΔVITIMER, the device regulates the FET gate voltage to actively limit the output current to the set ILIM level. The device will exit current limiting when the load current falls below ILIM. Equation 7 can be used to calculate the RILIM value for a desired current limit.

Equation 7. GUID-2DE0C858-548C-42BE-8C6D-6F1EE1854526-low.gif
Note:

Leaving the ILIM pin Open sets the overcurrent threshold to zero and causes the FET to shut off as soon as any load current is detected. Shorting the ILIM pin to ground at any point during normal operation is detected as a fault and the part shuts down. The ILIM pin Short to GND fault detection circuit doesn't allow any load current higher than ICB to flow through the device. This ensures robust eFuse behavior even under single point failure conditions. Refer to the Fault Response section for details on the device behavior after a fault.

GUID-20231011-SS0I-HMPS-Z2KB-BQSM5BBR3WZK-low.svg Figure 8-5 Active Current Limiter Response

The duration for which load transients are allowed can be adjusted using an appropriate capacitor value from ITIMER pin to ground. The transient overcurrent blanking interval can be calculated using Equation 8.

Equation 8. GUID-C2966E94-7F93-4DD2-865D-112A62177882-low.gif

Leave the ITIMER pin open to allow the part to activate the current limit with the minimum possible delay. Refer to ITIMER Functional Mode Summary for more details.

Note:

1. Current limiting based on RILIM is active during startup for both Current Limit and Circuit Breaker variants. In case the startup current exceeds ILIM, the device regulates the current to the set limit. However, during startup the current limit is engaged without waiting for the ITIMER delay.

2. The active current limit block employs a foldback mechanism during start-up based on the output voltage (VOUT). When VOUT is below the foldback threshold (VFB), the current limit threshold is further lowered as compared to the steady-state setting.

3. Shorting the ITIMER pin to ground is detected as a fault and the part shuts down. This ensures robust eFuse behavior even in case of single point failure conditions. Refer to the Fault Response section for details on the device behavior after a fault.

4. Larger ITIMER capacitors take longer to charge during start-up and may lead to incorrect fault assertion if the ITIMER voltage is still below the pin short detection threshold after the device has reached steady state. To avoid this, it is recommended to limit the maximum ITIMER capacitor to the value suggested by the equation below.

GUID-C3AD1CF8-9EEB-4EE7-9E6C-974617EBD36C-low.gif
GUID-52A2EFA2-7545-42CC-9770-DAE8FF39F7FA-low.gif
Where

  • tGHI is the time taken by the device to reach steady state
  • tD,ON is the device turn-on delay
  • Cdvdt is the dVdt capacitance
  • Idvdt is the dVdt charging current

It is possible to avoid incorrect ITIMER pin fault assertion and achieve higher ITIMER intervals if needed by increasing the dVdt capacitor value accordingly, but at the expense of higher start-up time.

During current regulation, the output voltage will drop resulting in increased device power dissipation across the FET. If the device internal temperature (TJ) exceeds the thermal shutdown threshold (TSD), the FET is turned off. See Overtemperature Protection (OTP) for more details on device response to overtemperature.