JAJSQU2A August   2023  – October 2023 TPS25983

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Protection (UVLO and UVP)
      2. 8.3.2 Overvoltage Protection (OVP)
      3. 8.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.3.1 Slew Rate and Inrush Current Control (dVdt)
        2. 8.3.3.2 Circuit Breaker
        3. 8.3.3.3 Active Current Limiting
        4. 8.3.3.4 Short-Circuit Protection
      4. 8.3.4 Overtemperature Protection (OTP)
      5. 8.3.5 Analog Load Current Monitor (IMON)
      6. 8.3.6 Power Good (PG)
      7. 8.3.7 Reverse Current Blocking FET Driver
      8. 8.3.8 Fault Response
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Standby Power Rail Protection in Datacenter Servers
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
        2. 9.2.2.2 Setting the Current Limit Threshold: RILIM Selection
        3. 9.2.2.3 Setting the Undervoltage and Overvoltage Lockout Set Point
        4. 9.2.2.4 Choosing the Current Monitoring Resistor: RIMON
        5. 9.2.2.5 Setting the Output Voltage Ramp Time (TdVdt)
          1. 9.2.2.5.1 Case 1: Start-Up Without Load: Only Output Capacitance COUT Draws Current
          2. 9.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance COUT and Load Draw Current
        6. 9.2.2.6 Setting the Transient Overcurrent Blanking Interval (tITIMER)
        7. 9.2.2.7 Setting the Auto-Retry Delay and Number of Retries
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Optical Module Power Rail Path Protection
        1. 9.3.1.1 Design Requirements
        2. 9.3.1.2 Device Selection
        3. 9.3.1.3 External Component Settings
        4. 9.3.1.4 Voltage Drop
        5. 9.3.1.5 Application Curves
      2. 9.3.2 Input Protection for 12-V Rail Applications: PCIe Cards, Storage Interfaces, and DC Fans
      3. 9.3.3 Priority Power MUXing
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 Output Short-Circuit Measurements
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.3 Priority Power MUXing

Applications having two energy sources such as PCIe cards, tablets, and portable battery powered equipment require preference of one source to another. For example, mains power (wall-adapter) has the priority over the internal battery back-up power. These applications demand for switchover from mains power to backup power only when main input voltage falls below a user-defined threshold. The TPS25983 devices provide a simple design for priority power multiplexing needs.

Figure 9-17 shows a typical priority power multiplexing implementation using TPS25983 devices. When the primary (priority) power source (IN1) is present and above the undervoltage (UVLO) threshold, the primary path device path powers the OUT bus irrespective of which auxiliary supply voltage condition. The device in auxiliary path is held in off condition by forcing the OVLO pin to high using the EN/UVLO signal of the primary path device. Once the primary supply voltage falls below the user-defined undervoltage threshold (UVLO), the primary path device is turned off. At the same the auxiliary, the auxiliary path device turns on and starts delivering power to the load. In this configuration, supply overvoltage protection is not available on both channels.

GUID-20230731-SS0I-K9TD-V5T4-0X2BKTCPJ9RN-low.svg Figure 9-17 Two Devices, Priority Power MUX Configuration

The PG pins of the devices can be used as a digital indication to identify which of the two supplies is active and delivering power to the load.

A key consideration in power MUXing applications is the minimum voltage the output bus droops to during the switchover from one supply to another. This in turn depends on multiple factors including the output load current (ILOAD), output bus hold-up capacitance (COUT) and switchover time (tSW).

While switching from primary supply (VIN1) to auxiliary supply (VIN2) or vice versa, the minimum bus voltage can be calculated using Equation 30. Here, the maximum switchover time (tSW) is the time taken by the device to turn on and start delivering power to the load, which is equal to the device turn on time (tON), which includes the turn on delay (tD,ON) and rise time (tR) determined by the dVdt capacitor (CdVdt) and bus voltage.

Equation 30. GUID-20200925-CA0I-SQNJ-14QF-QB6JTKXK4KMV-low.gif

Figure 9-18 and Figure 9-19 illustrate the power MUXing behavior.

GUID-20230731-SS0I-GXN6-S0G9-BQ00KDWBCLKD-low.svgFigure 9-18 TPS25983 Power MUX, Switchover From Primary to Auxiliary Supply
GUID-20230731-SS0I-9PLT-28KW-VGPLBWCDBD1H-low.svgFigure 9-19 TPS25983 Power MUX, Switchover From Auxiliary to Primary Supply
Note:
  1. Power MUXing can be accomplished either between two similar rails (such as 12-V primary and 12-V auxiliary, 3.3-V primary and 3.3-V auxiliary) or between dissimilar rails (such as 12-V primary and 5-V auxiliary, or vice versa).
  2. For power MUXing cases with skewed voltage combinations, care must be taken to design circuit components on EN/UVLO, OVLO pins for the lower voltage channel devices such that the absolute-maximum ratings on those pins are not exceeded when higher voltage is present on the other channel. Also, the dVdt pin capacitor rating must be chosen based on the highest of the two supplies. Refer to Recommended Operating Conditions table for more details.
  3. Using a series resistance between EN/UVLO pin of primary path eFuse and the OVLO pin of the auxiliary path eFuse is recommended. The value of the series resistor must be at least 10 times higher than the bottom resistor of the ladder on the EN/UVLO pin of the primary path eFuse.