JAJSMF5 データシート

JAJSMF5B september 2022 – june 2023 TPS25990

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RQP|26
- MPQF569A

サーマルパッド・メカニカル・データ

発注情報

9.2.2 Detailed Design Procedure

Determining the number of eFuse devices to be used in parallel
As the design must have PMBus® functionality or interface for telemetry, control, and configuration, the TPS25990 eFuse must be used as a primary device in parallel with TPS25985x eFuse(s) as secondary devices in order to support the required steady-state thermal design current. By factoring in a small variation in the junction to ambient thermal resistance (R_θJA), each TPS25990 eFuse and TPS25985x eFuse is rated at maximum RMS currents of 50 A and 60 A respectively with a maximum junction temperature of 125 °C. Therefore, Equation 26 can be used to calculate the number of TPS25985x eFuses (N-1) to be in parallel with a TPS25990 eFuse to support the maximum steady state DC load current (I_LOAD(max)), for which the solution must be designed.
Equation 26. $(N - 1) \geq \frac{(I_{O U T (m a x)} - 50)}{60}$
According to Table 9-69, I_OUT(max) is 333 A. Therefore, one (1) TPS25990 and five (5) TPS25985x eFuses are connected in parallel to support the desired steady-state load current.
Setting up the primary and secondary devices in a parallel combination of TPS25990 and TPS25985x eFuses
The TPS25990 functions as a primary device by default. By connecting the MODE pin of all the TPS25985x eFuses to GND, they are configured as secondary devices.

Selecting the C_DVDT capacitor to control the output slew rate and start-up time

For a robust design, the junction temperature of the device must be kept below the absolute maximum rating during both dynamic (start-up) and steady-state conditions. Typically, dynamic power stresses are orders of magnitude greater than static stresses, so it is crucial to establish the right start-up time and inrush current limit for the capacitance in the system and the associated loads to avoid thermal shutdown during start-up.

Table 9-2 summarizes the formulas for calculating the average inrush power loss on the eFuses in the presence of different loads during start-up if the power good (PG) signal is not used to turn on all the downstream loads.

Table 9-2 Calculation of Average Power Loss During Inrush

Type of Loads During Start-Up	Expressions to Calculate the Average Inrush Power Loss
Only output capacitor of C_LOAD (µF)	Equation 27. $\frac{V_{I N}^{2} C_{L O A D}}{2 T_{s s}}$
Output capacitor of C_LOAD (µF) and constant resistance of R_{LOAD(Startup)} (Ω) with turn-ON threshold of V_RTH (V)	Equation 28. $\frac{V_{I N}^{2} C_{L O A D}}{2 T_{s s}} + \frac{V_{I N}^{2}}{R_{L O A D (S t a r t u p)}} [\frac{1}{6} - \{\frac{1}{2} {(\frac{V_{R T H}}{V_{I N}})}^{2}\} + \{\frac{1}{3} {(\frac{V_{R T H}}{V_{I N}})}^{3}\}]$
Output capacitor of C_LOAD (µF) and constant current of I_{LOAD(Startup)} (A) with turn-ON threshold of V_CTH (V)	Equation 29. $\frac{V_{I N}^{2} C_{L O A D}}{2 T_{s s}} + V_{I N} I_{L O A D (S t a r t u p)} [\frac{1}{2} - (\frac{V_{C T H}}{V_{I N}}) + \{\frac{1}{2} {(\frac{V_{C T H}}{V_{I N}})}^{2}\}]$
Output capacitor of C_LOAD (µF) and constant power of P_{LOAD(Startup)} (W) with turn-ON threshold of V_PTH (V)	Equation 30. $\frac{V_{I N}^{2} C_{L O A D}}{2 T_{s s}} + P_{L O A D (S t a r t u p)} [\ln (\frac{V_{P T H}}{V_{I N}}) + (\frac{V_{P T H}}{V_{I N}}) - 1]$

Where V_IN is the input voltage and T_ss is the start-up time.

With the different combinations of loads during start-up, the total average inrush power loss (P_INRUSH) can be calculated using the formulas described in Table 9-2. For a successful start-up, the system must satisfy the condition stated in Equation 31.

Equation 31.

P_{I N R U S H} (W) \sqrt{T_{s s} (s)} < \{8 + 12 (N - 1)\}

Where N denotes the total number of eFuses in parallel and 8 W√s and 12 W√s are the safe operating area (SOA) limits of a TPS25990 eFuse and a TPS25985x eFuse respectively. This equation can be used to obtain the maximum allowed T_ss.

Note:

TI recommends to use a T_ss in the range of 5 ms to 120 ms to prevent start-up issues.

A capacitor (C_DVDT) must be added at the TPS25990 DVDT pin to GND to set the required value of T_ss as calculated above. Equation 32 is used to compute the value of C_DVDT. The DVDT pins of all the eFuses in a parallel chain must be connected together.

Equation 32.

C_{D V D T} (p F) = \frac{42000 \times k}{V_{I N} (V) / T_{s s} (m s)}

Refer to Section 8.3.4.1 section for more details. In this design example, C_LOAD = 50 mF, R_{LOAD(Startup)} = 0.48 Ω, V_RTH = 0 V, V_IN = 12 V, and T_ss = 10 ms. P_INRUSH is calculated to be 410 W using the equations provided in the Table 9-2. It is verified that the system satisfies the condition stated in Equation 31 and therefore capable of having a successful start-up. If Equation 31 does not hold true, start-up loads or T_ss must be tuned to prevent the chances of thermal shutdown during start-up. Using V_IN = 12 V, T_ss = 10 ms, k= 1, and Equation 32, the required C_DVDT value can be calculated to be 35 nF. The closest standard value of C_DVDT is 33 nF with 10% tolerance and DC voltage rating of 25 V.

Note:

In some systems, there can be active load circuits (for example, DC-DC converters) with low turn-on threshold voltages which can start drawing power before the eFuse has completed the inrush sequence. This action can cause additional power dissipation inside the eFuse during start-up and can lead to thermal shutdown. TI recommends using the Power Good (PG) pin of the eFuse to enable and disable the load circuit. This action ensures that the load is turned on only when the eFuse has completed its start-up and is ready to deliver full power without the risk of hitting thermal shutdown.

Selecting the V_IREF to set the reference voltage for overcurrent protection and active current sharing
The reference voltage (V_IREF) for overcurrent protection and active current sharing will be at 1 V by default. However, it can be programmed via PMBus® using the VIREF register if another reference voltage is needed in the range of 0.3 V to 1.2 V. When the voltage at the IMON pin (V_IMON) is used as an input to an ADC to monitor the system current or to implement the Platform Power Control (Intel PSYS) functionality inside the VR controller, V_IREF must be set to half of the maximum voltage range of the ISYS_IN input of the controller. This action provides the necessary headroom and dynamic range for the system to accurately monitor the load current up to the fast-trip threshold (2 × I_OCP(TOTAL)). For improved noise immunity, place a 1 nF ceramic capacitor from the IREF pin to GND.
Note:
Maintain V_IREF within the recommended voltage to ensure proper operation of overcurrent detection circuit.

Selecting the R_IMON resistor to set the overcurrent (circuit-breaker) and fast-trip thresholds during steady-state
TPS25990 eFuse responds to the output overcurrent conditions during steady-state by turning off the output after a user-adjustable transient fault blanking interval. This eFuse continuously senses the total system current (I_OUT) and produces a proportional analog current output (I_IMON) on the IMON pin. This generates a voltage (V_IMON) across the IMON pin resistor (R_IMON) in response to the load current, which is defined as Equation 33.
Equation 33. $V_{I M O N} = I_{O U T} \times G_{I M O N} \times R_{I M O N}$
G_IMON is the current monitor gain (I_IMON : I_OUT), whose typical value is 18.18 µA/A. The overcurrent condition is detected by comparing the V_IMON against the V_IREF as a threshold. The circuit-breaker threshold during steady-state (I_OCP(TOTAL)) can be calculated using Equation 34.
Equation 34. $I_{O C P (T O T A L)} = \frac{V_{I R E F}}{G_{I M O N} \times R_{I M O N}}$
In this design example, I_OCP(TOTAL) is considered to be around 1.1 times I_OUT(max). Hence, I_OCP(TOTAL) is required to be set at 367 A, and R_IMON can be calculated to be 150 Ω with G_IMON as 18.18 µA/A and V_IREF as 1 V. The value of R_IMON is 150 Ω with 0.1% tolerance and power rating of 100 mW. This results in a circuit-breaker threshold of 367 A. For noise immunity, place a 22 pF ceramic capacitor from the IMON pin to GND.
Note:
The total system output current (I_OUT) must be considered when selecting R_IMON, not the current carried by each individual device.

Selecting the R_ILIM resistor to set the current limit and fast-trip thresholds during start-up and the active sharing threshold during steady-state
R_ILIM is used in setting up the active current sharing threshold during steady-state and the overcurrent limit during startup among the devices in a parallel chain. Each device continuously monitors the current flowing through it (I_DEVICE) and outputs a proportional analog output current on its own ILIM pin. This in turn produces a proportional voltage (V_ILIM) across the respective ILIM pin resistor (R_ILIM), which is expressed as Equation 35.
Equation 35. $V_{I L I M} = I_{D E V I C E} \times G_{I L I M} \times R_{I L I M}$
G_ILIM is the current monitor gain (I_ILIM : I_DEVICE), whose typical value is 18.18 μA/A.
- Active current sharing during steady-state: This mechanism operates only after the device reaches steady-state and acts independently by comparing its own load current information (V_ILIM) with the Active Current Sharing reference (CLREF_LIN) threshold, defined as Equation 36.
  Equation 36. ${C L R E F}_{L I N} = \frac{1.1 \times V_{I R E F}}{3}$
  The typical values of R_DSON for TPS25990 and TPS25985x eFuses are 0.79 mΩ and 0.59 mΩ respectively. Therefore, when one (1) TPS25990 eFuse and one (1) TPS25985x eFuse are in parallel, it is expected that the TPS25990 eFuse will carry 0.75 times the current flowing through the TPS25985x eFuse in steady-state. Therefore, R_{LIM(TPS25990)} must be calculated using Equation 37 to define the active current sharing threshold as 3×I_OCP(TOTAL)/(4N-1) for TPS25990 eFuse, where N is the total number of devices in parallel (1 × TPS25990 + (N - 1) × TPS25985x). Whereas, Equation 38 needs to be followed to obtain the value of R_{LIM(TPS25985)} in setting up the active current sharing threshold as 4×I_OCP(TOTAL)/(4N-1) for each TPS25985x eFuse. Using N = 6, R_IMON = 150 Ω, and Equation 37, R_{ILIM(TPS25990)} can be calculated to be 421.6 Ω. The closest standard value of 422 Ω with 0.1% tolerance and power rating of 100 mW resistance is selected as R_{ILIM(TPS25990)} for TPS25990 eFuse. Using Equation 38, R_{ILIM(TPS25985)} is obtained as 316.2 Ω.The closest standard value of 316 Ω with 0.1% tolerance and power rating of 100 mW resistances are selected as R_{ILIM(TPS25985)} for five (5) TPS25985x eFuses.
  Equation 37. $R_{I L I M (T P S 25990)} = \frac{1.1 \times (4 N - 1) \times R_{I M O N}}{9}$
  Equation 38. $R_{I L I M (T P S 25985)} = \frac{1.1 \times (4 N - 1) \times R_{I M O N}}{12}$
  Note:
  To determine the value of R_ILIM, Equation 39 must be used if a different threshold for active current sharing (I_LIM(ACS)) is desired.
  Equation 39. $R_{I L I M} = \frac{1.1 \times V_{I R E F}}{3 \times G_{I L I M} \times I_{L I M (A C S)}}$
  When computing the current limit threshold during start-up in the next sub-section, ensure to use this R_ILIM value.
- Overcurrent limit during start-up: During inrush, the overcurrent condition for each device is detected by comparing its own load current information (V_ILIM) with a scaled reference voltage as depicted in Equation 40.
  Equation 40. ${C L R E F}_{S A T} = \frac{0.7 \times V_{I R E F}}{3}$
  The current limit threshold during start-up can be calculated using Equation 41.
  Equation 41. $I_{I L I M (S t a r t u p)} = \frac{{C L R E F}_{S A T}}{G_{I L I M} \times R_{I L I M}}$
  By using a R_{ILIM(TPS25990)} value of 422 Ω, the start-up current is limited to 30 A for TPS25990 with V_IREF of 1 V. Whereas, the start-up current is limited to 40 A for TPS25985x with V_IREF of 1 V using a R_{ILIM(TPS25985)} value of 316 Ω. Hence, the total start-up current limit becomes ~230 A for this design example.
  Note:
  The active current limit block employs a foldback mechanism during start-up based on V_OUT. When V_OUT is below the foldback threshold (V_FB) of 2 V, the current limit threshold is further lowered.

Selecting the overcurrent blanking timer duration (t_{OC_TIMER})
The overcurrent blanking timer duration (t_{OC_TIMER}) for the entire parallel chain is controlled by TPS25990 and is set to 2.18 ms by default. However, it can be programmed via PMBus® using the OC_TIMER (E6h) register to a different value in the range of 0 ms to 27.8 ms in 100 μs steps. The ITIMER pin for all the secondary TPS25985x devices must be left open.

Selecting the resistors to set the undervoltage lockout threshold
The undervoltage lockout (UVLO) threshold is adjusted by employing the external voltage divider network of R₁ and R₂ connected between IN, EN/UVLO, and GND pins of the device as described in Undervoltage protection section. The resistor values required for setting up the UVLO threshold are calculated using Equation 42.
Equation 42. $V_{I N (U V)} = V_{U V L O (R)} \frac{R_{1} + R_{2}}{R_{2}}$
To minimize the input current drawn from the power supply, TI recommends using higher resistance values for R₁ and R₂. The current drawn by R₁ and R₂ from the power supply is I_R12 = V_IN / (R₁ + R₂). However, the leakage currents due to external active components connected to the resistor string can add errors to these calculations. So, the resistor string current, I_R12 must be 20 times greater than the leakage current at the EN/UVLO pin (I_ENLKG). From the device electrical specifications, I_ENLKG is 0.1 µA (maximum) and UVLO rising threshold V_UVLO(R) = 1.2 V. From the design requirements, V_INUVLO = 10.8 V. First choose the value of R₁ = 1 MΩ and use Equation 13 to calculate R₂ = 125 kΩ. Use the closest standard 1% resistor values: R₁ = 1 MΩ and R₂ = 124 kΩ. For noise reduction, place a 1 nF ceramic capacitor across the EN/UVLO pin and GND.

Selecting the R-C filter between VIN and VDD for TPS25990 and TPS25985x
VDD pin is intended to power the internal control circuitry of the eFuse with a filtered and stable supply, not affected by system transients. Therefore, use an R (10 Ω) – C (2.2 µF) filter from the input supply (IN pin) to the VDD pin. This helps to filter out the supply noises and to hold up the controller supply during severe faults such as short-circuit at the output. In a parallel chain, this R-C filter must be employed for each device.

Selecting the pullup resistors and power supplies for SWEN, PG and FLT pins
FLT, PG, and CMPOUT are open drain outputs. If these logic signals are used, the corresponding pins must be pulled up to the appropriate voltages (< 5 V) through 10 kΩ pull-up resistances.
Note:
- SWEN pin must be pulled up to a voltage in the range of 2.5 V to 5 V through a 100-kΩ resistance. This pullup power supply must be generated from the input to the eFuse and available before the eFuse is enabled as discussed in Section 9.3, without which the eFuse does not start up.
- There can be some threshold or timing mismatches between devices leading to PG assertion in a staggered manner. Therefore, it is advisable to connect the PG pins of all the devices in parallel. This will ensure that the combined PG signal becomes high only after all devices have released their PG pulldowns.

Selecting the pullup resistors for PMBus® SCL, SDA, and SMBA# lines
The SCL, SDA, and SMBA# lines can be pulled up to potentials less than 5 V in general with pull-up resistors of 10 kΩ. However, to obtain the appropriate values of these pull-up resistors in accordance with the system specifications, please refer to I2C Bus Pullup Resistor Calculation.
Configuring the PMBus® target device address
Place appropriate resistors across ADDR0 and ADDR1 to GND or leave these pins floating or connect them to GND as described in Section 8.3.14.1 to set the preferred device address. To improve the noise immunity for correct address decoding, connect 10 pF ceramic capacitors in parallel with the resistors on ADDR0 and ADDR1.
Selection of TVS diode at input and Schottky diode at output
In the case of a short circuit and overload current limit when the device interrupts a large amount of current instantaneously, the input inductance generates a positive voltage spike on the input, whereas the output inductance creates a negative voltage spike on the output. The peak amplitudes of these voltage spikes (transients) are dependent on the value of inductance in series with the input or output of the device. Such transients can exceed the absolute maximum ratings of the device and eventually lead to failures due to electrical overstress (EOS) if appropriate steps are not taken to address this issue. Typical methods for addressing this issue include:
1. Minimize lead length and inductance into and out of the device.
2. Use a large PCB GND plane.
3. Addition of the Transient Voltage Suppressor (TVS) diodes to clamp the positive transient spike at the input.
4. Using Schottky diodes across the output to absorb negative spikes.
Refer to TVS Clamping in Hot-Swap Circuits and Selecting TVS Diodes in Hot-Swap and ORing Applications for details on selecting an appropriate TVS diode and the number of TVS diodes to be in parallel to effectively clamp the positive transients at the input below the absolute maximum ratings of the IN pin (20 V). These TVS diodes also help to limit the transient voltage at the IN pin during the Hot Plug event. Four (4) SMDJ12A are used in parallel in this design example.
Note:
Maximum Clamping Voltage V_C specification of the selected TVS diode at I_pp (10/1000 μs) (V) must be lower than the absolute maximum rating of the power input (IN) pin for safe operation of the eFuse.
Selection of the Schottky diodes must be based on the following criteria:
- The non-repetitive peak forward surge current (I_FSM) of the selected diode must be more than the fast-trip threshold (2 × I_OCP(TOTAL)). Two or more Schottky diodes in parallel must be used if a single Schottky diode is unable to meet the required I_FSM rating. Equation 43 calculates the number of Schottky diodes (N_Schottky) that must be used in parallel.
  Equation 43. $N_{S c h o t t k y} > \frac{2 \times I_{O C P (T O T A L)}}{I_{F S M}}$
- Forward Voltage Drop (V_F) at near to I_FSM must be as small as possible. Ideally, the negative transient voltage at the OUT pin must be clamped within the absolute maximum rating of the OUT pin (–1 V).
- DC Blocking Voltage (V_RM) must be more than the maximum input operating voltage.
- Leakage current (I_R) must be as small as possible.
Three (3) SBR10U45SP5 are used in parallel in this design example.

Selecting C_IN and C_OUT
TI recommends to add ceramic bypass capacitors to help stabilize the voltages on the input and output. The value of C_IN must be kept small to minimize the current spike during hot-plug events. For each device, 0.1 µF of C_IN is a reasonable target. Because C_OUT does not get charged during hot-plug, a larger value such as 2.2 µF can be used at the OUT pin of each device.