JAJSGA2F September   2018  – June 2021 TPS2663

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Hot Plug-In and In-Rush Current Control
        1. 9.3.1.1 Thermal Regulation Loop
      2. 9.3.2  PGOOD and PGTH
        1. 9.3.2.1 PGTH as VOUT Sensing Input
      3. 9.3.3  Undervoltage Lockout (UVLO)
      4. 9.3.4  Overvoltage Protection (OVP)
      5. 9.3.5  Input Reverse Polarity Protection (B_GATE, DRV)
      6. 9.3.6  Reverse Current Protection
      7. 9.3.7  Overload and Short Circuit Protection
        1. 9.3.7.1 Overload Protection
          1. 9.3.7.1.1 Active Current Limiting at 1x IOL, (TPS26630 and TPS26632 Only)
          2. 9.3.7.1.2 Active Current Limiting with 2x IOL Pulse Current Support, (TPS26631, TPS26633, TPS26635 and TPS26636 Only)
        2. 9.3.7.2 Short Circuit Protection
          1. 9.3.7.2.1 Start-Up With Short-Circuit On Output
      8. 9.3.8  Output Power Limiting, PLIM (TPS26632, TPS26633, TPS26635 and TPS26636 Only)
      9. 9.3.9  Current Monitoring Output (IMON)
      10. 9.3.10 FAULT Response ( FLT)
      11. 9.3.11 IN_SYS, IN, OUT and GND Pins
      12. 9.3.12 Thermal Shutdown
      13. 9.3.13 Low Current Shutdown Control (SHDN)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Power Path Protection in a PLC System
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Programming the Current-Limit Threshold—R(ILIM) Selection
        2. 10.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 10.2.2.3 Output Buffer Capacitor – COUT
        4. 10.2.2.4 PGTH Set Point
        5. 10.2.2.5 Setting Output Voltage Ramp Time—(tdVdT)
          1. 10.2.2.5.1 Support Component Selections— RPGOOD and C(IN)
        6. 10.2.2.6 Selecting Q1, Q2 and TVS Clamp for Surge Protection
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Simple 24-V Power Supply Path Protection
      2. 10.3.2 Priority Power MUX Operation
      3. 10.3.3 Input Protection for a Compact 24-V Auxiliary Power Supply for Servo Drives
    4. 10.4 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGE|24
  • PWP|20
サーマルパッド・メカニカル・データ

7.5 Electrical Characteristics

–40°C ≤ TA = TJ ≤ +125°C, 4.5 V < V(IN_SYS) = V(IN) < 60 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD =  FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY VOLTAGE
V(IN_SYS)Operating input voltage4.560V
IQ(ON)Supply currentEnabled: V( SHDN) = 2 V1.381.7mA
IQ(OFF)V( SHDN) = 0 V2160µA
I(GND)Ground current during reverse polarityV(IN_SYS) = –24V, V(IN) = Floating, V(OUT) = 0 V144200µA
V(OVC)Over voltage clampTPS26632, TPS26633, TPS26636 Only, V(IN_SYS) > 35 V, I(OUT) = 1 mA3232.835V
TPS26635 Only, V(IN_SYS) > 40 V, I(OUT) = 1 mA35.736.639V
UNDERVOLTAGE LOCKOUT (UVLO) INPUT
V(INSYS_UVLO)Factory set V(IN_SYS) undervoltage trip level trip levelV(IN_SYS) rising, V(UVLO) = 0 V15.115.4615.9V
V(IN_SYS) falling, V(UVLO) = 0 V1414.4715.1V
V(SEL_UVLO)Internal UVLO select threshold180210240mV
V(UVLOR)UVLO threshold voltage, rising1.1761.21.224V
V(UVLOF)UVLO threshold voltage, falling1.091.1221.15V
I(UVLO)UVLO Input leakage current0 V ≤ V(UVLO) ≤ 60 V–1508150nA
OVERVOLTAGE PROTECTION (OVP) INPUT
V(IN_SYS_OVP)Factory set V(IN_SYS) overvoltage trip level trip levelV(IN_SYS) rising, V(OVP) = 0 V33.234.3335.4V
V(IN_SYS) falling, V(OVP) = 0 V32.733.8935V
V(SEL_OVP)Internal OVP select threshold180210240mV
V(OVPR)over-voltage threshold voltage, rising1.1761.21.224V
V(OVPF)over-voltage threshold voltage, falling1.091.1221.15V
I(OVP)OVP Input leakage current0 V ≤ V(OVP) ≤ 4 V–1500150nA
CURRENT LIMIT PROGRAMMING (ILIM)
I(OL)Over Load current limitR(ILIM) = 30 kΩ, V(IN) – V(OUT) = 1 V0.540.60.66A
R(ILIM) = 9 kΩ, V(IN) –  V(OUT) = 1 V1.8422.16A
R(ILIM) = 4.02 kΩ, V(IN) – V(OUT) = 1 V4.1854.54.815A
R(ILIM) = 3 kΩ, V(IN) – V(OUT) = 1 V5.5866.42A
I(OL_Pulse)Transient Pulse Over current limit3 kΩ < R(ILIM) < 30 kΩ, TPS26631, TPS26633, TPS26635 and TPS26636 Only2xI(OL)A
I(FASTRIP)Fast-trip comparator thresholdTPS26630 and TPS26632 Only2xI(OL)A
I(FASTRIP)Fast-trip comparator thresholdTPS26631, TPS26633,TPS26635 and TPS26636 Only3xI(OL)A
I(SCP)Short Circuit Protect current45A
OUTPUT POWER LIMITING CONTROL (PLIM) INPUT – TPS26632, TPS26633, TPS26635 and TPS26636 ONLY
V(SEL_PLIM)Power Limit Feature select threshold160217240mV
I(PLIM)PLIM sourcing currentV(PLIM) = 0 V4.45.025.6µA
P(PLIM)Max Output powerR(PLIM) = 100 kΩ94100106W
R(PLIM) = 150 kΩ (1)141.9151160.1W
B_GATE (BLOCKING FET GATE DRIVER)
V(B_GATE)B_GATE clamp voltageV(B_GATE) – V(IN_SYS)8.310.2314V
I(B_GATE)Blocking FET Gate drive currentV(B_GATE) – V(IN_SYS) = 1 V1619.423µA
Rpd_BGATEB_GATE Pull down resistance80010101200kΩ
V(DRV_OH)DRV logic high levelV(DRV) – V(IN_SYS), C(DRV) ≤ 50 pF34.255.2V
PASS FET OUTPUT (OUT)
RONIN to OUT total ON resistance0.6 A ≤ I(OUT) ≤ 6 A,TJ = 25°C2630.4434.5mΩ
RONIN to OUT total ON resistance0.6 A ≤ I(OUT) ≤ 6 A,TJ = 85°C3345mΩ
RONIN to OUT total ON resistance0.6 A ≤ I(OUT) ≤ 6 A, –40°C ≤ TJ ≤ +125°C1930.4453mΩ
Ilkg(OUT)OUT leakage during input supply brownoutV(IN_SYS) = 0 V, V(OUT) = 24 V, V(IN) = Floating, V( SHDN) = 2V, Sinking–100µA
V(REVTH)V(IN_SYS) – V(OUT) threshold for reverse protection comparator, rising–20–15–9mV
V(FWDTH)V(IN_SYS) – V(OUT) threshold for reverse protection comparator, falling455767mV
OUTPUT RAMP CONTROL (dVdT)
I(dVdT)dVdT charging currentV(dVdT) = 0 V1.77522.225µA
GAIN(dVdT)dVdT to OUT gainV(OUT) /V(dVdT)23.52526V/V
V(dVdTmax)dVdT maximum capacitor voltage3.84.174.75V
R(dVdT)dVdT discharging resistance1016.626.6Ω
LOW IQ SHUTDOWN ( SHDN) INPUT
V( SHDN)Open circuit voltageI( SHDN) = 0.1 µA2.482.73.3V
V(SHUTF)SHDN threshold voltage for low IQ shutdown, falling0.8V
V(SHUTR)SHDN threshold rising2V
I( SHDN)Leakage currentV( SHDN) = 0 V–10µA
CURRENT MONITOR OUTPUT (IMON)
GAIN(IMON)Gain factor I(IMON):I(OUT)0.6 A ≤ I(OUT) ≤ 2 A25.6627.930.14µA/A
2 A ≤ I(OUT) ≤ 6 A26.2227.929.58µA/A
FAULT FLAG ( FLT): ACTIVE LOW
R( FLT)FLT Pull-down resistance3670130Ω
I( FLT)FLT Input leakage current0 V ≤ V( FLT) ≤ 60 V–1506150nA
POWER GOOD (PGOOD)
R(PGOOD)PGOOD Pull-down resistance3670130Ω
I(PGOOD)PGOOD Input leakage current0 V ≤ V(PGOOD) ≤ 60 V–150150nA
POSITIVE INPUT FOR POWER GOOD COMPARATOR (PGTH)
V(PGTHR)PGTH threshold voltage, rising1.1761.21.224V
V(PGTHF)PGTH threshold voltage, falling1.091.1231.15V
I(PGOOD)PGTH input leakage current0 V ≤ V(PGTH) ≤ 60 V–150150nA
THERMAL PROTECTION
T(J_REG)Thermal regulation set point136145154°C
T(TSD)Thermal shutdown (TSD) threshold, rising165°C
T(TSDhyst)TSD hysteresis11°C
MODE
MODE_SELMode selectionMODE = OpenLatch
MODE = Short to GNDAuto – Retry
(1) Parameter guaranteed by design and characterization, not tested in production