JAJSKH0C April   2023  – February 2024 TPS274C65

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1.     7
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 SPI Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Diagrams
      2. 8.3.2 SPI Mode Operation
        1. 8.3.2.1 Diagnostic Bit Behavior
      3. 8.3.3 Programmable Current Limit
        1. 8.3.3.1 Inrush Current Handling
      4. 8.3.4 DO_EN Feature
      5. 8.3.5 Protection Mechanisms
        1. 8.3.5.1 Overcurrent Protection
        2. 8.3.5.2 Short Circuit Protection
          1. 8.3.5.2.1 VS During Short-to-Ground
        3. 8.3.5.3 Inductive-Load Switching-Off Clamp
        4. 8.3.5.4 Inductive Load Demagnetization
        5. 8.3.5.5 Thermal Shutdown
        6. 8.3.5.6 Undervoltage protection on VS
        7. 8.3.5.7 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)
        8. 8.3.5.8 Power-Up and Power-Down Behavior
        9. 8.3.5.9 Reverse Current Blocking
      6. 8.3.6 Diagnostic Mechanisms
        1. 8.3.6.1 Current Sense
          1. 8.3.6.1.1 RSNS Value
            1. 8.3.6.1.1.1 SNS Output Filter
        2. 8.3.6.2 Fault Indication
          1. 8.3.6.2.1 Current Limit Behavior
        3. 8.3.6.3 Short-to-Battery and Open-Load Detection
        4. 8.3.6.4 On-State Wire-Break Detection
        5. 8.3.6.5 Off State Wire-Break Detection
        6. 8.3.6.6 ADC
      7. 8.3.7 LED Driver
    4. 8.4 Device Functional Modes
      1. 8.4.1 OFF/POR
      2. 8.4.2 INIT
      3. 8.4.3 Active
    5. 8.5 TPS274C65BS Available Registers List
    6. 8.6 TPS274C65 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IEC 61000-4-5 Surge
        2. 9.2.2.2 Loss of GND
        3. 9.2.2.3 Paralleling Channels
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.5.9 Reverse Current Blocking

Reverse current occurs when VVS<VOUT. In this case, current will flow from VOUTx to VS. Reverse current can be caused by miswiring at the output, or a capacitive or inductive load can cause inverse current. For example, if there is a significant amount of load capacitance and the VS node has a transient droop, VOUTx may be greater than VS. The VSdroop may be caused by inrush current from a different load. Similarly load/supply faults and inductive loads can cause supply to be pushed up as well. Another application is to provide protection when output connection to supply (miswiring) occurs when the input power supply is not available or connected. The device monitors VS and VOUT to provide true reverse current blocking when a reverse condition or input power failure condition is detected.

To prevent reverse current flow, TPS274C65AS integrates a NMOS gate driver that drives an external blocking FET. The blocking FET is enabled as soon as the device is enabled and VVS > VS_UVP. When a reverse current condition is detected such as VOUT － VVS > VRCB_R, the blocking FET gets disabled to prevent unwanted reverse currents and signaled through RVRS_BLK_FLT and FLT. Once off, TPS274C65AS has the hysteresis implemented to keep the RCB FET off as long as VOUT － VVS < VRCB_F. After tRCB_comp_reset timer expired, the RCB FET is enabled to check if the reverse current condition has cleared, and the comparator threshold is reset from VRCB_F to VRCB_R. If VOUT － VVS > VRCB_Rcondition is met after the RCB FET is re-enabled, TPS274C65AS again turns off the RCB FET. During reverse current event, current sensing is not available, and ISNS and ADC register go to 0 mA.

In case the RCB FET needs to be kept off, the per channel RCB bit RCB_CHx can be turned low to keep the RCB FET off. However, the main FET needs to be off as well to avoid excessive heat through the RCB FET that can lead to the RCB FET damage. If there's no external RCB FET connected, RCB_DIS bit needs to be turned high , and the RCB pins need to be left floating. Each channel has RCB_CHx bit to configure the RCB FET to be always OFF or with normal RCB function as described above. Table 8-8 shows some example use cases for the RCB feature.

Table 8-8 Common Applications for RCB
Example Application RCB_DIS Per Channel RCB Comment
Digital Output Module but reverse current blocking function is not desired 1 RCB_CHx = X RCB pin left floating and not connected to the RCB FET.
Digital Output Module and reverse current blocking function is needed 0 RCB_CHx = 1 RCB pin connected to the RCB FET gate with normal RCB function.
Digital Input Ouput module with RCB FET used to conduct current in DI configuration 0 RCB_CHx = 0 RCB pin connected to the RCB FET gate with RCB FET always OFF. No RCB detection.
Digital Input Ouput module with the channel in Digital Output configuration 0 RCB_CHx = 1 RCB pin connected to the FET gate with normal RCB function.
GUID-20231017-SS0I-HQPJ-LMGZ-HKHWX3JF21HV-low.svg Figure 8-30 Reverse Current Blocking