JAJSKH0C April   2023  – February 2024 TPS274C65

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1.     7
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 SPI Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Diagrams
      2. 8.3.2 SPI Mode Operation
        1. 8.3.2.1 Diagnostic Bit Behavior
      3. 8.3.3 Programmable Current Limit
        1. 8.3.3.1 Inrush Current Handling
      4. 8.3.4 DO_EN Feature
      5. 8.3.5 Protection Mechanisms
        1. 8.3.5.1 Overcurrent Protection
        2. 8.3.5.2 Short Circuit Protection
          1. 8.3.5.2.1 VS During Short-to-Ground
        3. 8.3.5.3 Inductive-Load Switching-Off Clamp
        4. 8.3.5.4 Inductive Load Demagnetization
        5. 8.3.5.5 Thermal Shutdown
        6. 8.3.5.6 Undervoltage protection on VS
        7. 8.3.5.7 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)
        8. 8.3.5.8 Power-Up and Power-Down Behavior
        9. 8.3.5.9 Reverse Current Blocking
      6. 8.3.6 Diagnostic Mechanisms
        1. 8.3.6.1 Current Sense
          1. 8.3.6.1.1 RSNS Value
            1. 8.3.6.1.1.1 SNS Output Filter
        2. 8.3.6.2 Fault Indication
          1. 8.3.6.2.1 Current Limit Behavior
        3. 8.3.6.3 Short-to-Battery and Open-Load Detection
        4. 8.3.6.4 On-State Wire-Break Detection
        5. 8.3.6.5 Off State Wire-Break Detection
        6. 8.3.6.6 ADC
      7. 8.3.7 LED Driver
    4. 8.4 Device Functional Modes
      1. 8.4.1 OFF/POR
      2. 8.4.2 INIT
      3. 8.4.3 Active
    5. 8.5 TPS274C65BS Available Registers List
    6. 8.6 TPS274C65 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IEC 61000-4-5 Surge
        2. 9.2.2.2 Loss of GND
        3. 9.2.2.3 Paralleling Channels
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Switching Characteristics

VS = 6 V to 36 V, TJ = –40°C to +125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX
UNIT
tDR CHx Turnon delay time VS = 24 V, RL = 48 Ω 50% of EN to 10% of VOUT 5 18 25 µs
tDF CHx Turnoff delay time VS = 24 V, RL = 48 Ω 50% of EN to 90% of VOUT 16 24 33 µs
SR2R VOUTx rising slew rate VS = 24 V, 25% to 75% of VOUT,
RL = 48 Ω, 		 1 1.6 2.2 V/µs
SR2F VOUTx falling slew rate VS = 24 V, 75% to 25% of VOUT,
RL = 48 Ω, 		 1 1.4 1.8 V/µs
fmax Maximum PWM frequency 1 kHz
tON CHx Turnon time VS = 24 V, RL = 48 Ω  50% of EN to 90% of VOUT 33 42 µs
tOFF CHx Turnoff time VS = 24 V, RL = 48 Ω  50% of EN to 10% of VOUT 46 57 µs
tON - tOFF CHx Turnon and off matching 1ms ON time switch enable pulse VBB = 24 V, RL = 48 Ω –41 –7 23 µs
tON - tOFF CHx Turnon and off matching 100-µs OFF time switch enable pulse, VS = 24 V, RL = 48 Ω, F = fmax –41 –7 23 µs
tON - tOFF CHxTurnon and off matching 100-µs ON time switch enable pulse, VS = 24 V, RL = 48 Ω, F = fmax –41 –7 23 µs
ΔPWM CHx PWM accuracy - average load current 200-µs enable pulse, VS = 24 V, RL = 48 Ω 
F = fmax		 –20 20 %