JAJSKH0C April   2023  – February 2024 TPS274C65

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1.     7
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 SPI Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Diagrams
      2. 8.3.2 SPI Mode Operation
        1. 8.3.2.1 Diagnostic Bit Behavior
      3. 8.3.3 Programmable Current Limit
        1. 8.3.3.1 Inrush Current Handling
      4. 8.3.4 DO_EN Feature
      5. 8.3.5 Protection Mechanisms
        1. 8.3.5.1 Overcurrent Protection
        2. 8.3.5.2 Short Circuit Protection
          1. 8.3.5.2.1 VS During Short-to-Ground
        3. 8.3.5.3 Inductive-Load Switching-Off Clamp
        4. 8.3.5.4 Inductive Load Demagnetization
        5. 8.3.5.5 Thermal Shutdown
        6. 8.3.5.6 Undervoltage protection on VS
        7. 8.3.5.7 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)
        8. 8.3.5.8 Power-Up and Power-Down Behavior
        9. 8.3.5.9 Reverse Current Blocking
      6. 8.3.6 Diagnostic Mechanisms
        1. 8.3.6.1 Current Sense
          1. 8.3.6.1.1 RSNS Value
            1. 8.3.6.1.1.1 SNS Output Filter
        2. 8.3.6.2 Fault Indication
          1. 8.3.6.2.1 Current Limit Behavior
        3. 8.3.6.3 Short-to-Battery and Open-Load Detection
        4. 8.3.6.4 On-State Wire-Break Detection
        5. 8.3.6.5 Off State Wire-Break Detection
        6. 8.3.6.6 ADC
      7. 8.3.7 LED Driver
    4. 8.4 Device Functional Modes
      1. 8.4.1 OFF/POR
      2. 8.4.2 INIT
      3. 8.4.3 Active
    5. 8.5 TPS274C65BS Available Registers List
    6. 8.6 TPS274C65 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IEC 61000-4-5 Surge
        2. 9.2.2.2 Loss of GND
        3. 9.2.2.3 Paralleling Channels
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

Table 5-1 Pin Functions – Version AS and BS Do not connect for pins labeled DNC
PIN TYPE(1) DESCRIPTION
NO. TPS274C65AS, 
TPS274C65ASH		 TPS274C65BS
1 READY DNC(3) O Logic low output indicating the IC is ready for SPI data transmission (connect to GND pin of the IC with resistor).
2 FLT FLT O Fault output – on any (one or more) channel - open drain, needs to be pulled up to VDD pin.
3 DO_EN DO_EN I Setting this pin low would disable all of the outputs. Set high to enable SPI based output Internal pull-down.
4 VDD(2) VDD(2) P Logic Supply Input(2).
5, 21 GND GND — Device ground.
6 ISNS DNC(3) O SNS current output – use a parallel RC network to the GND pin of the IC.
7 SDO SDO O SPI Data Output from the device.
8 SDI SDI I SPI device (secondary) data input.
9 SCLK SCLK O SPI Clock Input.
10 CS CS I SPI Chip select.
11 RCB3 DNC(3) O Gate connection for reverse current blocking FET Ch3.
12, 13 OUT3 OUT3 O Output voltage for channel 3.
14–17 VS VS P 24V Switch Supply input to the IC.
18, 19 OUT4 OUT4 O Output voltage for channel 4.
20 RCB4 DNC(3) O Gate connection for reverse current blocking FET Ch4.
22 LEDOUT1 DNC(3) O LED matrix select driver.
23 LEDOUT2 DNC(3) O LED matrix select driver.
24 LEDOUT3 DNC(3) O LED matrix select driver.
25 LEDOUT4 DNC(3) O LED matrix select driver.
26 DNC(3) DNC(3) — Do not connect.
27 DNC(3) DNC(3) — Do not connect.
28 DSPI DSPI I Configure the device in daisy chain SPI mode when the pin is pulled HI.
29 REG_EN REG_EN I Internal Regulator Enable pin, float to enable. Tie to GND to disable and use an external supply input to VDD.
30 ADDCFG ADDCFG I SPI IC Address Configuration pin – set the 3-bit address of each IC (up to 8 on one board) with a resistor to GND pin of the IC. Leave floating if using Daisy Chain mode.
31 RCB2 DNC(3) O Gate connection for reverse current blocking FET Ch2.
32, 33 OUT2 OUT2 O Output voltage for channel 2.
34–37 VS VS P 24V Switch Supply input to the IC.
38, 39 OUT1 OUT1 O Output voltage for channel 1.
40 RCB1 DNC(3) O Gate connection for reverse current blocking FET Ch1.
Exposed Pad GND GND I Connected to GND pin of the IC.
(1) I = input, O = output, P = power.
(2) When the device is configured to support an external regulator connected to VDD, it is required that the
supply input for the external regulator is derived from the same VS supply of TPS274C65 as shown in the Typical Application Schematic.
(3) Do not connect for pins labeled DNC.