JAJSOU6 October   2023 TPS2HCS10-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Recommended Connections for Unused Pins
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Mechanisms
        1. 8.3.1.1 Programmable Fuse Protection
        2. 8.3.1.2 Thermal Shutdown
        3. 8.3.1.3 Overcurrent Protection And Capacitive Load Charging
        4. 8.3.1.4 Reverse Battery
      2. 8.3.2 Diagnostic Mechanisms
        1. 8.3.2.1 VOUT Short-to-Battery and Open-Load
          1. 8.3.2.1.1 Detection With Channel Output (FET) Enabled
          2. 8.3.2.1.2 Detection With Channel Output Disabled
        2. 8.3.2.2 Digital Current Sense Output
          1. 8.3.2.2.1 RSNS Value and Accuracy / Resolution of Current Measurement
            1. 8.3.2.2.1.1 High Accuracy Load Current Sense
            2. 8.3.2.2.1.2 SNS Output Filter
        3. 8.3.2.3 Output Voltage and FET Temperature Sensing
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 SLEEP
      3. 8.4.3 CONFIG/ACTIVE
      4. 8.4.4 Battery Supply Input (VBB) Under-voltage
      5. 8.4.5 LOW POWER MODE (LPM) State
      6. 8.4.6 LIMP HOME state
      7. 8.4.7 SPI Mode Operation
    5. 8.5 TPS2HC10S Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Thermal Considerations
        2. 9.2.2.2 Configuring the Capacitive Charging Mode
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1 Application Information

Figure 9-1 shows the schematic of a typical application of the TPS2HC10S. It includes all standard external components. This section of the data sheet discusses the considerations in implementing commonly required application functionality. The circuit assumes no reverse polarity protection on the input supply, so additional components for protection are required.

Special Note on Prototype Silicon

The prototype silicon is not the final production silicon and is offered as preview. The following limitations exist in the prototype version.

  1. There is a variation of ADC output in the range of +/-12 codes (for current sense) or +/- 4 codes for voltage sensing for a constant load current or output voltage and can affect the ADC readings at the low end of ADC range. The reason is due to excessive noise on the ADC supply input, which will be corrected in the production release.

  2. The prototype device does not reliably support turn-off of the outputs (FETs) in case of a loss of GND. The production version will support FET turn-off with loss-of-GND.

  3. The prototype device may see a high current flow and potential pin damage into the device upon unclamped negative transient similar to ISO-7637 Pulse 1 at the VBB supply input. The production version will be robust against these transients.

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With the ground protection network, the device ground will be offset relative to the micro-controller ground. The same power supply (5 V (recommended) or 3.3V) source should be used for the controller (MCU) I/O as well as the VDD supply input to the TPS2HCS10-Q1 device.
Figure 9-1 System Diagram
Table 9-1 Recommended External Components
COMPONENT TYPICAL VALUE PURPOSE
RPROT1 1 – 2.2 kΩ Protect micro-controller and device SPI pins
RPROT2 10 kΩ Protect micro-controller and device GPIO pins
RSNS 1 kΩ Translate the sense current into sense voltage for ADC input
CSNS 1 nF - 4.7 nF Low-pass filter for the ADC input.
Input TVS +36 V and –20 V Suppress voltage transients (one for the module)
DGND, BAS21 / Schottky Diode Limit Current during reverse voltage on supply events. A low forward voltage diode is recommended and a Schottky diode is suggested when the low voltage supply VDD is 3.3V. (Note that we recommend 5V supply for the prototype silicon)
RGND 4.7 kΩ Maintain ground potential during negative output voltage excursions
RVDD 220 Ω Limit current to the device during transients
CVDD 470 nF VDD supply voltage stability to system ground.
CVBB1 4.7 nF to Device GND Filtering of transients (for example, ESD, ISO7637-2) and improved emissions.
CVBB2 100 – 2200-nF to Module GND Stabilize the input supply and filter out low frequency noise.
COUT 22 nF Filtering of voltage transients (for example, ESD, ISO7637-2).