JAJSM88A november   2022  – april 2023 TPS36-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 デバイスの比較
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Supervisor
      2. 8.3.2 Window Watchdog Timer
        1. 8.3.2.1 tWC (Close Window) Timer
        2. 8.3.2.2 tWO (Open Window) Timer
        3. 8.3.2.3 Watchdog Enable Disable Operation
        4. 8.3.2.4 tSD Watchdog Start Up Delay
        5. 8.3.2.5 SET Pin Behavior
      3. 8.3.3 Manual RESET
      4. 8.3.4 RESET and WDO Output
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 CRST Delay
        1. 9.1.1.1 Factory-Programmed Reset Delay Timing
        2. 9.1.1.2 Adjustable Capacitor Timing
      2. 9.1.2 Watchdog Window Functionality
        1. 9.1.2.1 Factory-Programmed watchdog Timing
        2. 9.1.2.2 Adjustable Capacitor Timing
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Monitoring Microcontroller Supply and Watchdog During Operational and Sleep Modes
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Setting Voltage Threshold
          2. 9.2.1.2.2 Determining Window Timings During Operation and Sleep Modes
          3. 9.2.1.2.3 Meeting the Minimum Reset Delay
          4. 9.2.1.2.4 Setting the Watchdog Window
          5. 9.2.1.2.5 Calculating the RESET Pullup Resistor
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 デバイスの比較

図 5-1 に、TPS36-Q1 のデバイス命名規則 を示します。可能なすべての出力タイプ、スレッショルド電圧オプション、ウォッチドッグ時間オプション、および出力アサート遅延オプションの詳細については、 TPS36-Q1 プログラマブル・ウィンドウ・ウォッチドッグ・タイマ付き高精度電圧スーパーバイザ TPS36-Q1 車載用 Nano IQ 高精度電圧監視回路、高精度ウィンドウ・ウォッチドッグ・タイマ付き TPS36-Q1 車載用 Nano IQ 高精度電圧監視回路、高精度ウィンドウ・ウォッチドッグ・タイマ付き 特長 特長 アプリケーション アプリケーション 概要 概要 Table of Contents Table of Contents Revision History Revision History デバイスの比較 デバイスの比較 Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics Timing Requirements Timing Requirements Switching Characteristics Switching Characteristics Timing Diagrams Timing Diagrams Typical Characteristics Typical Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagrams Functional Block Diagrams Feature Description Feature Description Voltage Supervisor Voltage Supervisor Window Watchdog Timer Window Watchdog Timer tWC (Close Window) Timer tWC (Close Window) Timer tWO (Open Window) Timer tWO (Open Window) Timer Watchdog Enable Disable Operation Watchdog Enable Disable Operation tSD Watchdog Start Up Delay tSD Watchdog Start Up Delay SET Pin Behavior SET Pin Behavior Manual RESET Manual RESET RESET and WDO Output RESET and WDO Output Device Functional Modes Device Functional Modes Application and Implementation Application and Implementation Application Information Application Information CRST Delay CRST Delay Factory-Programmed Reset Delay Timing Factory-Programmed Reset Delay Timing Adjustable Capacitor Timing Adjustable Capacitor Timing Watchdog Window Functionality Watchdog Window Functionality Factory-Programmed watchdog Timing Factory-Programmed watchdog Timing Adjustable Capacitor Timing Adjustable Capacitor Timing Typical Applications Typical Applications Design 1: Monitoring Microcontroller Supply and Watchdog During Operational and Sleep Modes Design 1: Monitoring Microcontroller Supply and Watchdog During Operational and Sleep Modes Design Requirements Design Requirements Detailed Design Procedure Detailed Design Procedure Setting Voltage Threshold Setting Voltage Threshold Determining Window Timings During Operation and Sleep Modes Determining Window Timings During Operation and Sleep Modes Meeting the Minimum Reset Delay Meeting the Minimum Reset Delay Setting the Watchdog Window Setting the Watchdog Window Calculating the RESET Pullup Resistor Calculating the RESET Pullup Resistor Power Supply Recommendations Power Supply Recommendations Layout Layout Layout Guidelines Layout Guidelines Layout Example Layout Example Device and Documentation Support Device and Documentation Support ドキュメントの更新通知を受け取る方法 ドキュメントの更新通知を受け取る方法 サポート・リソース サポート・リソース Trademarks Trademarks 静電気放電に関する注意事項 静電気放電に関する注意事項 用語集 用語集 Mechanical, Packaging, and Orderable Information Mechanical, Packaging, and Orderable Information 重要なお知らせと免責事項 重要なお知らせと免責事項 TPS36-Q1 車載用 Nano IQ 高精度電圧監視回路、高精度ウィンドウ・ウォッチドッグ・タイマ付き TPS36-Q1 車載用 Nano IQ 高精度電圧監視回路、高精度ウィンドウ・ウォッチドッグ・タイマ付きTPS36-Q1車載用 高精度電圧監視回路、ウィンドウ・ 特長 A 20221210 事前情報から量産データのリリースに変更 yes 下記内容で AEC-Q100 認定済み デバイス温度グレード 1：動作時周囲温度範囲：-40℃～125℃ 工場出荷時にプログラム済みまたはユーザーがプログラム可能なウォッチドッグ・タイムアウト ±10% 精度のタイマ (最大値) 工場出荷時にプログラム済みのクローズ・ウィンドウ：1msec～100sec 工場出荷時にプログラム済みまたはユーザーがプログラム可能なリセット遅延 ±10% 精度のタイマ (最大値) 工場出荷時にプログラム済みのオプション：2msec～10sec 入力電圧範囲：VDD = 1.04V～6.0V 固定スレッショルド電圧 (VIT-)：1.05V～5.4V スレッショルド電圧は 50mV 刻みで利用可能 1.2% の電圧スレッショルド精度 (最大値) ヒステリシス内蔵 (VHYS)：5% (標準値) 超低電源電流：IDD = 250nA (標準値) オープン・ドレイン、プッシュプル、アクティブ Low 出力 各種のプログラマビリティ・オプション： ウォッチドッグ・イネーブル / ディセーブル ウォッチドッグ・スタートアップ遅延：遅延なし～10 秒 オープン・ウィンドウとクローズ・ウィンドウの比率オプション：1 倍～511 倍 ラッチ付き出力オプション MR 機能のサポート 特長 A 20221210 事前情報から量産データのリリースに変更 yes A 20221210 事前情報から量産データのリリースに変更 yes A 20221210 事前情報から量産データのリリースに変更 yes A20221210事前情報から量産データのリリースに変更yes 下記内容で AEC-Q100 認定済み デバイス温度グレード 1：動作時周囲温度範囲：-40℃～125℃ 工場出荷時にプログラム済みまたはユーザーがプログラム可能なウォッチドッグ・タイムアウト ±10% 精度のタイマ (最大値) 工場出荷時にプログラム済みのクローズ・ウィンドウ：1msec～100sec 工場出荷時にプログラム済みまたはユーザーがプログラム可能なリセット遅延 ±10% 精度のタイマ (最大値) 工場出荷時にプログラム済みのオプション：2msec～10sec 入力電圧範囲：VDD = 1.04V～6.0V 固定スレッショルド電圧 (VIT-)：1.05V～5.4V スレッショルド電圧は 50mV 刻みで利用可能 1.2% の電圧スレッショルド精度 (最大値) ヒステリシス内蔵 (VHYS)：5% (標準値) 超低電源電流：IDD = 250nA (標準値) オープン・ドレイン、プッシュプル、アクティブ Low 出力 各種のプログラマビリティ・オプション： ウォッチドッグ・イネーブル / ディセーブル ウォッチドッグ・スタートアップ遅延：遅延なし～10 秒 オープン・ウィンドウとクローズ・ウィンドウの比率オプション：1 倍～511 倍 ラッチ付き出力オプション MR 機能のサポート 下記内容で AEC-Q100 認定済み デバイス温度グレード 1：動作時周囲温度範囲：-40℃～125℃ 工場出荷時にプログラム済みまたはユーザーがプログラム可能なウォッチドッグ・タイムアウト ±10% 精度のタイマ (最大値) 工場出荷時にプログラム済みのクローズ・ウィンドウ：1msec～100sec 工場出荷時にプログラム済みまたはユーザーがプログラム可能なリセット遅延 ±10% 精度のタイマ (最大値) 工場出荷時にプログラム済みのオプション：2msec～10sec 入力電圧範囲：VDD = 1.04V～6.0V 固定スレッショルド電圧 (VIT-)：1.05V～5.4V スレッショルド電圧は 50mV 刻みで利用可能 1.2% の電圧スレッショルド精度 (最大値) ヒステリシス内蔵 (VHYS)：5% (標準値) 超低電源電流：IDD = 250nA (標準値) オープン・ドレイン、プッシュプル、アクティブ Low 出力 各種のプログラマビリティ・オプション： ウォッチドッグ・イネーブル / ディセーブル ウォッチドッグ・スタートアップ遅延：遅延なし～10 秒 オープン・ウィンドウとクローズ・ウィンドウの比率オプション：1 倍～511 倍 ラッチ付き出力オプション MR 機能のサポート 下記内容で AEC-Q100 認定済み デバイス温度グレード 1：動作時周囲温度範囲：-40℃～125℃ 工場出荷時にプログラム済みまたはユーザーがプログラム可能なウォッチドッグ・タイムアウト ±10% 精度のタイマ (最大値) 工場出荷時にプログラム済みのクローズ・ウィンドウ：1msec～100sec 工場出荷時にプログラム済みまたはユーザーがプログラム可能なリセット遅延 ±10% 精度のタイマ (最大値) 工場出荷時にプログラム済みのオプション：2msec～10sec 入力電圧範囲：VDD = 1.04V～6.0V 固定スレッショルド電圧 (VIT-)：1.05V～5.4V スレッショルド電圧は 50mV 刻みで利用可能 1.2% の電圧スレッショルド精度 (最大値) ヒステリシス内蔵 (VHYS)：5% (標準値) 超低電源電流：IDD = 250nA (標準値) オープン・ドレイン、プッシュプル、アクティブ Low 出力 各種のプログラマビリティ・オプション： ウォッチドッグ・イネーブル / ディセーブル ウォッチドッグ・スタートアップ遅延：遅延なし～10 秒 オープン・ウィンドウとクローズ・ウィンドウの比率オプション：1 倍～511 倍 ラッチ付き出力オプション MR 機能のサポート 下記内容で AEC-Q100 認定済み デバイス温度グレード 1：動作時周囲温度範囲：-40℃～125℃ デバイス温度グレード 1：動作時周囲温度範囲：-40℃～125℃ デバイス温度グレード 1：動作時周囲温度範囲：-40℃～125℃工場出荷時にプログラム済みまたはユーザーがプログラム可能なウォッチドッグ・タイムアウト ±10% 精度のタイマ (最大値) 工場出荷時にプログラム済みのクローズ・ウィンドウ：1msec～100sec ±10% 精度のタイマ (最大値) 工場出荷時にプログラム済みのクローズ・ウィンドウ：1msec～100sec ±10% 精度のタイマ (最大値)工場出荷時にプログラム済みのクローズ・ウィンドウ：1msec～100sec工場出荷時にプログラム済みまたはユーザーがプログラム可能なリセット遅延 ±10% 精度のタイマ (最大値) 工場出荷時にプログラム済みのオプション：2msec～10sec ±10% 精度のタイマ (最大値) 工場出荷時にプログラム済みのオプション：2msec～10sec ±10% 精度のタイマ (最大値)工場出荷時にプログラム済みのオプション：2msec～10sec入力電圧範囲：VDD = 1.04V～6.0VDD固定スレッショルド電圧 (VIT-)：1.05V～5.4V スレッショルド電圧は 50mV 刻みで利用可能 1.2% の電圧スレッショルド精度 (最大値) ヒステリシス内蔵 (VHYS)：5% (標準値) IT- スレッショルド電圧は 50mV 刻みで利用可能 1.2% の電圧スレッショルド精度 (最大値) ヒステリシス内蔵 (VHYS)：5% (標準値) スレッショルド電圧は 50mV 刻みで利用可能1.2% の電圧スレッショルド精度 (最大値)ヒステリシス内蔵 (VHYS)：5% (標準値)HYS超低電源電流：IDD = 250nA (標準値)DDオープン・ドレイン、プッシュプル、アクティブ Low 出力各種のプログラマビリティ・オプション： ウォッチドッグ・イネーブル / ディセーブル ウォッチドッグ・スタートアップ遅延：遅延なし～10 秒 オープン・ウィンドウとクローズ・ウィンドウの比率オプション：1 倍～511 倍 ラッチ付き出力オプション ウォッチドッグ・イネーブル / ディセーブル ウォッチドッグ・スタートアップ遅延：遅延なし～10 秒 オープン・ウィンドウとクローズ・ウィンドウの比率オプション：1 倍～511 倍 ラッチ付き出力オプション ウォッチドッグ・イネーブル / ディセーブルウォッチドッグ・スタートアップ遅延：遅延なし～10 秒オープン・ウィンドウとクローズ・ウィンドウの比率オプション：1 倍～511 倍ラッチ付き出力オプション MR 機能のサポートMR アプリケーション オンボード・チャージャ (OBC) およびワイヤレス・チャージャ ドライバー監視 バッテリ管理システム (BMS) フロント・カメラ サラウンド・ビュー・システムの ECU アプリケーション オンボード・チャージャ (OBC) およびワイヤレス・チャージャ ドライバー監視 バッテリ管理システム (BMS) フロント・カメラ サラウンド・ビュー・システムの ECU オンボード・チャージャ (OBC) およびワイヤレス・チャージャ ドライバー監視 バッテリ管理システム (BMS) フロント・カメラ サラウンド・ビュー・システムの ECU オンボード・チャージャ (OBC) およびワイヤレス・チャージャ ドライバー監視 バッテリ管理システム (BMS) フロント・カメラ サラウンド・ビュー・システムの ECU オンボード・チャージャ (OBC) およびワイヤレス・チャージャ オンボード・チャージャ (OBC) およびワイヤレス・チャージャ ドライバー監視 ドライバー監視 バッテリ管理システム (BMS) バッテリ管理システム (BMS) フロント・カメラ フロント・カメラ サラウンド・ビュー・システムの ECU サラウンド・ビュー・システムの ECU 概要 TPS36-Q1 は、超低消費電力 (標準値 250nA) のデバイスであり、高精度電圧監視回路を備え、プログラム可能なウィンドウ・ウォッチドッグ・タイマを搭載しています。 TPS36-Q1 は、低電圧監視のための広いスレッショルド・レベルをサポートしており、規定された温度範囲全体にわたって 1.2% の精度を達成しています。 TPS36-Q1 は、さまざまなアプリケーションに対応する多くの機能を備えた高精度ウィンドウ・ウォッチドッグ・タイマを提供します。クローズ・ウィンドウ・タイマは、工場出荷時にプログラムするか、または、外付けコンデンサを使用してユーザーがプログラムするか、いずれかが可能です。オープン・ウィンドウとクローズ・ウィンドウの比率は、ロジック・ピンの組み合わせを使用して動作中でも変更できます。また、このウォッチドッグは、イネーブル / ディセーブル、スタートアップ遅延、独立 WDO ピン・オプションなどの独自の機能も備えています。 RESET または WDO 遅延は、工場出荷時にプログラムされるデフォルトの遅延設定で設定するか、または外付けコンデンサでプログラムできます。また、このデバイスはラッチ付き出力動作も備えており、監視回路またはウォッチドッグのフォルトがクリアされるまで出力がラッチされます。 TPS36-Q1 は、 TPS3852-Q1 デバイス・ファミリに代わる性能アップグレード製品です。TPS36-Q1 は、小型の 8 ピン SOT-23 パッケージで供給されます。 製品情報 部品番号 パッケージ #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE 本体サイズ (公称) TPS36-Q1 DDF (8) 2.90mm × 1.60mm 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 代表的なアプリケーション回路 概要 TPS36-Q1 は、超低消費電力 (標準値 250nA) のデバイスであり、高精度電圧監視回路を備え、プログラム可能なウィンドウ・ウォッチドッグ・タイマを搭載しています。 TPS36-Q1 は、低電圧監視のための広いスレッショルド・レベルをサポートしており、規定された温度範囲全体にわたって 1.2% の精度を達成しています。 TPS36-Q1 は、さまざまなアプリケーションに対応する多くの機能を備えた高精度ウィンドウ・ウォッチドッグ・タイマを提供します。クローズ・ウィンドウ・タイマは、工場出荷時にプログラムするか、または、外付けコンデンサを使用してユーザーがプログラムするか、いずれかが可能です。オープン・ウィンドウとクローズ・ウィンドウの比率は、ロジック・ピンの組み合わせを使用して動作中でも変更できます。また、このウォッチドッグは、イネーブル / ディセーブル、スタートアップ遅延、独立 WDO ピン・オプションなどの独自の機能も備えています。 RESET または WDO 遅延は、工場出荷時にプログラムされるデフォルトの遅延設定で設定するか、または外付けコンデンサでプログラムできます。また、このデバイスはラッチ付き出力動作も備えており、監視回路またはウォッチドッグのフォルトがクリアされるまで出力がラッチされます。 TPS36-Q1 は、 TPS3852-Q1 デバイス・ファミリに代わる性能アップグレード製品です。TPS36-Q1 は、小型の 8 ピン SOT-23 パッケージで供給されます。 製品情報 部品番号 パッケージ #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE 本体サイズ (公称) TPS36-Q1 DDF (8) 2.90mm × 1.60mm 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 代表的なアプリケーション回路 TPS36-Q1 は、超低消費電力 (標準値 250nA) のデバイスであり、高精度電圧監視回路を備え、プログラム可能なウィンドウ・ウォッチドッグ・タイマを搭載しています。 TPS36-Q1 は、低電圧監視のための広いスレッショルド・レベルをサポートしており、規定された温度範囲全体にわたって 1.2% の精度を達成しています。 TPS36-Q1 は、さまざまなアプリケーションに対応する多くの機能を備えた高精度ウィンドウ・ウォッチドッグ・タイマを提供します。クローズ・ウィンドウ・タイマは、工場出荷時にプログラムするか、または、外付けコンデンサを使用してユーザーがプログラムするか、いずれかが可能です。オープン・ウィンドウとクローズ・ウィンドウの比率は、ロジック・ピンの組み合わせを使用して動作中でも変更できます。また、このウォッチドッグは、イネーブル / ディセーブル、スタートアップ遅延、独立 WDO ピン・オプションなどの独自の機能も備えています。 RESET または WDO 遅延は、工場出荷時にプログラムされるデフォルトの遅延設定で設定するか、または外付けコンデンサでプログラムできます。また、このデバイスはラッチ付き出力動作も備えており、監視回路またはウォッチドッグのフォルトがクリアされるまで出力がラッチされます。 TPS36-Q1 は、 TPS3852-Q1 デバイス・ファミリに代わる性能アップグレード製品です。TPS36-Q1 は、小型の 8 ピン SOT-23 パッケージで供給されます。 製品情報 部品番号 パッケージ #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE 本体サイズ (公称) TPS36-Q1 DDF (8) 2.90mm × 1.60mm 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 TPS36-Q1 は、超低消費電力 (標準値 250nA) のデバイスであり、高精度電圧監視回路を備え、プログラム可能なウィンドウ・ウォッチドッグ・タイマを搭載しています。 TPS36-Q1 は、低電圧監視のための広いスレッショルド・レベルをサポートしており、規定された温度範囲全体にわたって 1.2% の精度を達成しています。 TPS36-Q1高精度電圧監視回路を備え、ウィンドウ TPS36-Q1 は、低電圧監視のための広いスレッショルド・レベルをサポートしており、規定された温度範囲全体にわたって 1.2% の精度を達成しています。TPS36-Q1 TPS36-Q1 は、さまざまなアプリケーションに対応する多くの機能を備えた高精度ウィンドウ・ウォッチドッグ・タイマを提供します。クローズ・ウィンドウ・タイマは、工場出荷時にプログラムするか、または、外付けコンデンサを使用してユーザーがプログラムするか、いずれかが可能です。オープン・ウィンドウとクローズ・ウィンドウの比率は、ロジック・ピンの組み合わせを使用して動作中でも変更できます。また、このウォッチドッグは、イネーブル / ディセーブル、スタートアップ遅延、独立 WDO ピン・オプションなどの独自の機能も備えています。TPS36-Q1 RESET または WDO 遅延は、工場出荷時にプログラムされるデフォルトの遅延設定で設定するか、または外付けコンデンサでプログラムできます。また、このデバイスはラッチ付き出力動作も備えており、監視回路またはウォッチドッグのフォルトがクリアされるまで出力がラッチされます。 RESET または RESETWDO監視回路または TPS36-Q1 は、 TPS3852-Q1 デバイス・ファミリに代わる性能アップグレード製品です。TPS36-Q1 は、小型の 8 ピン SOT-23 パッケージで供給されます。TPS36-Q1 TPS3852-Q1 TPS3852-Q1TPS36-Q1 製品情報 部品番号 パッケージ #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE 本体サイズ (公称) TPS36-Q1 DDF (8) 2.90mm × 1.60mm 製品情報 部品番号 パッケージ #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE 本体サイズ (公称) TPS36-Q1 DDF (8) 2.90mm × 1.60mm 部品番号 パッケージ #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE 本体サイズ (公称) 部品番号 パッケージ #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE 本体サイズ (公称) 部品番号パッケージ #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE #GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE本体サイズ (公称) TPS36-Q1 DDF (8) 2.90mm × 1.60mm TPS36-Q1 DDF (8) 2.90mm × 1.60mm TPS36-Q1 TPS36-Q1DDF (8)2.90mm × 1.60mm 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。 代表的なアプリケーション回路 代表的なアプリケーション回路 代表的なアプリケーション回路 代表的なアプリケーション回路 Table of Contents yes Table of Contents yes yes yes Revision History yes November 2022 December 2022 * A Revision History yes November 2022 December 2022 * A yes November 2022 December 2022 * A yesNovember 2022December 2022*A デバイスの比較 に、TPS36-Q1 のデバイス命名規則 を示します。可能なすべての出力タイプ、スレッショルド電圧オプション、ウォッチドッグ時間オプション、および出力アサート遅延オプションの詳細については、 を参照してください。他のオプションの詳細と提供状況については、TI の販売代理店または TI の E2E フォーラム にお問い合わせください。 デバイスの命名規則 TPS36-Q1 に示すように、さまざまな機能セットを提供するピン互換デバイス・ファミリに属します。 ピン互換デバイス・ファミリ デバイス 電圧監視 ウォッチドッグのタイプ TPS35-Q1 あり タイムアウト TPS36-Q1 あり ウィンドウ TPS3435-Q1 なし タイムアウト TPS3436-Q1 なし ウィンドウ デバイスの比較 に、TPS36-Q1 のデバイス命名規則 を示します。可能なすべての出力タイプ、スレッショルド電圧オプション、ウォッチドッグ時間オプション、および出力アサート遅延オプションの詳細については、 を参照してください。他のオプションの詳細と提供状況については、TI の販売代理店または TI の E2E フォーラム にお問い合わせください。 デバイスの命名規則 TPS36-Q1 に示すように、さまざまな機能セットを提供するピン互換デバイス・ファミリに属します。 ピン互換デバイス・ファミリ デバイス 電圧監視 ウォッチドッグのタイプ TPS35-Q1 あり タイムアウト TPS36-Q1 あり ウィンドウ TPS3435-Q1 なし タイムアウト TPS3436-Q1 なし ウィンドウ に、TPS36-Q1 のデバイス命名規則 を示します。可能なすべての出力タイプ、スレッショルド電圧オプション、ウォッチドッグ時間オプション、および出力アサート遅延オプションの詳細については、 を参照してください。他のオプションの詳細と提供状況については、TI の販売代理店または TI の E2E フォーラム にお問い合わせください。 デバイスの命名規則 TPS36-Q1 に示すように、さまざまな機能セットを提供するピン互換デバイス・ファミリに属します。 ピン互換デバイス・ファミリ デバイス 電圧監視 ウォッチドッグのタイプ TPS35-Q1 あり タイムアウト TPS36-Q1 あり ウィンドウ TPS3435-Q1 なし タイムアウト TPS3436-Q1 なし ウィンドウ に、TPS36-Q1 のデバイス命名規則 を示します。可能なすべての出力タイプ、スレッショルド電圧オプション、ウォッチドッグ時間オプション、および出力アサート遅延オプションの詳細については、 を参照してください。他のオプションの詳細と提供状況については、TI の販売代理店または TI の E2E フォーラム にお問い合わせください。TPS36-Q1スレッショルド電圧オプション、E2E フォーラム デバイスの命名規則 デバイスの命名規則 TPS36-Q1 に示すように、さまざまな機能セットを提供するピン互換デバイス・ファミリに属します。TPS36-Q1 ピン互換デバイス・ファミリ デバイス 電圧監視 ウォッチドッグのタイプ TPS35-Q1 あり タイムアウト TPS36-Q1 あり ウィンドウ TPS3435-Q1 なし タイムアウト TPS3436-Q1 なし ウィンドウ ピン互換デバイス・ファミリ デバイス 電圧監視 ウォッチドッグのタイプ TPS35-Q1 あり タイムアウト TPS36-Q1 あり ウィンドウ TPS3435-Q1 なし タイムアウト TPS3436-Q1 なし ウィンドウ デバイス 電圧監視 ウォッチドッグのタイプ デバイス 電圧監視 ウォッチドッグのタイプ デバイス電圧監視ウォッチドッグのタイプ TPS35-Q1 あり タイムアウト TPS36-Q1 あり ウィンドウ TPS3435-Q1 なし タイムアウト TPS3436-Q1 なし ウィンドウ TPS35-Q1 あり タイムアウト TPS35-Q1 -Q1ありタイムアウト TPS36-Q1 あり ウィンドウ TPS36-Q1 -Q1ありウィンドウ TPS3435-Q1 なし タイムアウト TPS3435-Q1 -Q1なしタイムアウト TPS3436-Q1 なし ウィンドウ TPS3436-Q1 -Q1なしウィンドウ Pin Configuration and Functions Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option D
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Functions PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C PINOUT D CRST 3 3 — — I Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout period. See for more details. CWD 2 2 — — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details. GND 4 4 4 4 — Ground pin MR 1 — 2 — I Manual reset pin. A logic low on this pin asserts the RESET. See for more details. RESET 7 7 7 7 O Reset output. Connect RESET to VDD using a pull up resistance when using open drain output. RESET is asserted when the voltage at the VDD pin goes below the undervoltage threshold (VIT-) or MR pin is driven LOW. For pinout options which do not support independent WDO pin, RESET is also asserted for watchdog error. See for more details. SET0 5 1 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET1 — 5 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. VDD 8 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 2 I Logic input. Logic high input enables the watchdog monitoring feature. See for more details. WDI 6 6 3 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for RESET / WDO to not assert. See for more details. WDO — — — 6 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO asserts when a watchdog error occurs. WDO only asserts when RESET is high. When a watchdog error occurs, WDO asserts for the set RESET timeout delay (tD). When RESET is asserted, WDO is deasserted and watchdog functionality is disabled. See for more details. Pin Configuration and Functions Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option D
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Functions PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C PINOUT D CRST 3 3 — — I Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout period. See for more details. CWD 2 2 — — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details. GND 4 4 4 4 — Ground pin MR 1 — 2 — I Manual reset pin. A logic low on this pin asserts the RESET. See for more details. RESET 7 7 7 7 O Reset output. Connect RESET to VDD using a pull up resistance when using open drain output. RESET is asserted when the voltage at the VDD pin goes below the undervoltage threshold (VIT-) or MR pin is driven LOW. For pinout options which do not support independent WDO pin, RESET is also asserted for watchdog error. See for more details. SET0 5 1 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET1 — 5 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. VDD 8 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 2 I Logic input. Logic high input enables the watchdog monitoring feature. See for more details. WDI 6 6 3 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for RESET / WDO to not assert. See for more details. WDO — — — 6 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO asserts when a watchdog error occurs. WDO only asserts when RESET is high. When a watchdog error occurs, WDO asserts for the set RESET timeout delay (tD). When RESET is asserted, WDO is deasserted and watchdog functionality is disabled. See for more details. Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option D
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Functions PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C PINOUT D CRST 3 3 — — I Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout period. See for more details. CWD 2 2 — — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details. GND 4 4 4 4 — Ground pin MR 1 — 2 — I Manual reset pin. A logic low on this pin asserts the RESET. See for more details. RESET 7 7 7 7 O Reset output. Connect RESET to VDD using a pull up resistance when using open drain output. RESET is asserted when the voltage at the VDD pin goes below the undervoltage threshold (VIT-) or MR pin is driven LOW. For pinout options which do not support independent WDO pin, RESET is also asserted for watchdog error. See for more details. SET0 5 1 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET1 — 5 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. VDD 8 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 2 I Logic input. Logic high input enables the watchdog monitoring feature. See for more details. WDI 6 6 3 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for RESET / WDO to not assert. See for more details. WDO — — — 6 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO asserts when a watchdog error occurs. WDO only asserts when RESET is high. When a watchdog error occurs, WDO asserts for the set RESET timeout delay (tD). When RESET is asserted, WDO is deasserted and watchdog functionality is disabled. See for more details. Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option D
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View DDF Package, 8-Pin SOT-23, TPS36-Q1 Top ViewTPS36-Q1 Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View DDF Package, 8-Pin SOT-23, TPS36-Q1 Top ViewTPS36-Q1 Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View DDF Package, 8-Pin SOT-23, TPS36-Q1 Top ViewTPS36-Q1 Pin Configuration Option D
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View Pin Configuration Option D
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View DDF Package, 8-Pin SOT-23, TPS36-Q1 Top ViewTPS36-Q1 Pin Functions PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C PINOUT D CRST 3 3 — — I Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout period. See for more details. CWD 2 2 — — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details. GND 4 4 4 4 — Ground pin MR 1 — 2 — I Manual reset pin. A logic low on this pin asserts the RESET. See for more details. RESET 7 7 7 7 O Reset output. Connect RESET to VDD using a pull up resistance when using open drain output. RESET is asserted when the voltage at the VDD pin goes below the undervoltage threshold (VIT-) or MR pin is driven LOW. For pinout options which do not support independent WDO pin, RESET is also asserted for watchdog error. See for more details. SET0 5 1 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET1 — 5 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. VDD 8 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 2 I Logic input. Logic high input enables the watchdog monitoring feature. See for more details. WDI 6 6 3 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for RESET / WDO to not assert. See for more details. WDO — — — 6 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO asserts when a watchdog error occurs. WDO only asserts when RESET is high. When a watchdog error occurs, WDO asserts for the set RESET timeout delay (tD). When RESET is asserted, WDO is deasserted and watchdog functionality is disabled. See for more details. Pin Functions PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C PINOUT D CRST 3 3 — — I Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout period. See for more details. CWD 2 2 — — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details. GND 4 4 4 4 — Ground pin MR 1 — 2 — I Manual reset pin. A logic low on this pin asserts the RESET. See for more details. RESET 7 7 7 7 O Reset output. Connect RESET to VDD using a pull up resistance when using open drain output. RESET is asserted when the voltage at the VDD pin goes below the undervoltage threshold (VIT-) or MR pin is driven LOW. For pinout options which do not support independent WDO pin, RESET is also asserted for watchdog error. See for more details. SET0 5 1 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET1 — 5 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. VDD 8 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 2 I Logic input. Logic high input enables the watchdog monitoring feature. See for more details. WDI 6 6 3 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for RESET / WDO to not assert. See for more details. WDO — — — 6 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO asserts when a watchdog error occurs. WDO only asserts when RESET is high. When a watchdog error occurs, WDO asserts for the set RESET timeout delay (tD). When RESET is asserted, WDO is deasserted and watchdog functionality is disabled. See for more details. PIN NAME PIN NUMBER I/O DESCRIPTION PINOUT A PINOUT B PINOUT C PINOUT D PIN NAME PIN NUMBER I/O DESCRIPTION PIN NAMEPIN NUMBERI/ODESCRIPTION PINOUT A PINOUT B PINOUT C PINOUT D PINOUT APINOUT BPINOUT CPINOUT D CRST 3 3 — — I Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout period. See for more details. CWD 2 2 — — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details. GND 4 4 4 4 — Ground pin MR 1 — 2 — I Manual reset pin. A logic low on this pin asserts the RESET. See for more details. RESET 7 7 7 7 O Reset output. Connect RESET to VDD using a pull up resistance when using open drain output. RESET is asserted when the voltage at the VDD pin goes below the undervoltage threshold (VIT-) or MR pin is driven LOW. For pinout options which do not support independent WDO pin, RESET is also asserted for watchdog error. See for more details. SET0 5 1 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET1 — 5 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. VDD 8 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 2 I Logic input. Logic high input enables the watchdog monitoring feature. See for more details. WDI 6 6 3 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for RESET / WDO to not assert. See for more details. WDO — — — 6 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO asserts when a watchdog error occurs. WDO only asserts when RESET is high. When a watchdog error occurs, WDO asserts for the set RESET timeout delay (tD). When RESET is asserted, WDO is deasserted and watchdog functionality is disabled. See for more details. CRST 3 3 — — I Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout period. See for more details. CRST33——IProgrammable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout period. See for more details. CWD 2 2 — — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details. CWD22——IProgrammable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See for more details.close time GND 4 4 4 4 — Ground pin GND4444—Ground pin MR 1 — 2 — I Manual reset pin. A logic low on this pin asserts the RESET. See for more details. MR MR1—2—IManual reset pin. A logic low on this pin asserts the RESET. See for more details.RESET RESET 7 7 7 7 O Reset output. Connect RESET to VDD using a pull up resistance when using open drain output. RESET is asserted when the voltage at the VDD pin goes below the undervoltage threshold (VIT-) or MR pin is driven LOW. For pinout options which do not support independent WDO pin, RESET is also asserted for watchdog error. See for more details. RESET RESET7777OReset output. Connect RESET to VDD using a pull up resistance when using open drain output. RESET is asserted when the voltage at the VDD pin goes below the undervoltage threshold (VIT-) or MR pin is driven LOW. For pinout options which do not support independent WDO pin, RESET is also asserted for watchdog error. See for more details.RESETRESETIT-MRWDORESET SET0 5 1 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET05111ILogic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details.window ratios SET1 — 5 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details. SET1—555ILogic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see for more details.window ratios VDD 8 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. VDD8888ISupply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WD-EN — — 6 2 I Logic input. Logic high input enables the watchdog monitoring feature. See for more details. WD-EN——62ILogic input. Logic high input enables the watchdog monitoring feature. See for more details. WDI 6 6 3 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for RESET / WDO to not assert. See for more details. WDI6633IWatchdog input. A falling transition (edge) must occur at this pin during the open window in order for RESET / WDO to not assert. See for more details.during the open windowRESETWDO WDO — — — 6 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO asserts when a watchdog error occurs. WDO only asserts when RESET is high. When a watchdog error occurs, WDO asserts for the set RESET timeout delay (tD). When RESET is asserted, WDO is deasserted and watchdog functionality is disabled. See for more details. WDO WDO———6OWatchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO asserts when a watchdog error occurs. WDO only asserts when RESET is high. When a watchdog error occurs, WDO asserts for the set RESET timeout delay (tD). When RESET is asserted, WDO is deasserted and watchdog functionality is disabled. See for more details.WDOWDOWDORESETWDORESETDRESETWDO Specifications Absolute Maximum Ratings over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1 MIN MAX UNIT Voltage VDD –0.3 6.5 V Voltage CWD, CRST, WD–EN, SETx, WDI,  MR (2),  RESET (Push Pull), WDO (Push Pull) –0.3 VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 V   RESET (Open Drain),  WDO (Open Drain) –0.3 6.5 Current RESET,  WDO pin –20 20 mA Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 Operating ambient temperature, TA –40 125 ℃ Temperature Storage, Tstg –65 150 Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.  The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller As a result of the low dissipated power in this device, it is assumed that TJ = TA. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Voltage VDD (Active Low output) 0.9 6 V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD RESET (Open Drain) , WDO (Open Drain) 0 6 RESET (Open Drain) , WDO (Push Pull) 0 VDD Current RESET, WDO pin current –5 5 mA CRST CRST pin capacitor range 1.5 1800 nF CWD CWD pin capacitor range 1.5 1000 nF TA Operating ambient temperature –40 125 ℃ If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS36-Q1 UNIT DDF (SOT23-8) 8 PINS RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJB Junction-to-board thermal resistance 92.4 °C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJB Junction-to-board characterization parameter 91.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V VIT– Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1_SF1 VIT– = 1.05 V to 1.95 V –1.4 ±0.5 1.4 % VIT– = 2.0 V to 5.4 V –1.2 ±0.5 1.2 VHYS Hysteresis VIT– pin VIT– = 1.05 V to 5.4 V 3 5 7 % IDD Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF1 VDD = 2 VVIT– = 1.05 V to 1.95 V TA = –40℃ to 85℃  0.25 0.8 µA 0.25 3 VDD = 6 VVIT– = 1.05 V to 5.4 V TA = –40℃ to 85℃  0.25 0.8 0.25 3 VIL Low level input voltage WD–EN, WDI, SETx, MR (3) 0.3VDD V VIH High level input voltage WD–EN, WDI, SETx, MR (3) 0.7VDD V R MR Manual reset internal pull-up resistance 100 kΩ RESET / WDO (Open-drain active-low) VOL Low level output voltage  VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA 300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6VTA = –40℃ to 85℃ 10 30 nA VDD = VPULLUP = 6V 10 120 nA RESET / WDO (Push-pull active-low) VPOR Power on RESET voltage (5) VOL(max) = 300 mVIOUT(Sink) = 15 µA 900 mV VOL Low level output voltage  VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA 300 mV VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA 300 VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA 300 VOH High level output voltage  VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA 0.8VDD V VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA 0.8VDD VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mA 0.8VDD VIT– threshold voltage range from 1.05 V to 5.4 V in 50 mV steps. If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VPOR is the minimum VDD voltage level for a controlled output state Timing Requirements At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tGI_VIT– Glitch immunity VIT– 5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2_SF2 15 µs t MR_PW MR pin pulse duration to assert reset 100 ns tP-WD WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 500 ns tHD-WDEN WD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 200 µs tHD-SETx SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 150 µs tWC Watchdog close window time period Orderable Option TPS36xxxxB 0.8 1 1.2 ms Orderable Option TPS36xxxxC 4 5 6 Orderable Option TPS36xxxxD 9 10 11 Orderable Option TPS36xxxxE 18 20 22 Orderable Option TPS36xxxxF 45 50 55 Orderable Option TPS36xxxxG 90 100 110 Orderable Option TPS36xxxxH 180 200 220 Orderable Option TPS36xxxxI 0.9 1 1.1 s Orderable Option TPS36xxxxJ 1.26 1.4 1.54 Orderable Option TPS36xxxxK 1.44 1.6 1.76 Orderable Option TPS36xxxxL 9 10 11 Orderable Option TPS36xxxxM 45 50 55 Orderable Option TPS36xxxxN 90 100 110 tWO Watchdog open window time period SETx pin decide multipler n (n-1) X tWC ms Overdrive % = [(VDD/ VIT–) – 1] × 100% Not production tested Switching Characteristics At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTRT Startup delay(4)   500 µs tP_HL RESET detect delay for VDD falling below VIT– VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1_SF1 30 50 µs tSD Watchdog startup delay Orderable part number TPS36xA, TPS36xG 0 ms Orderable part number TPS36xB, TPS36xH 180 200 220 Orderable part number TPS36xC, TPS36xI 450 500 550 Orderable part number TPS36xD, TPS36xJ 0.9 1 1.1 s Orderable part number TPS36xE, TPS36xK 4.5 5 5.5 Orderable part number TPS36xF, TPS36xL 9 10 11 tD Reset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1_SF1 Orderable part number TPS36xxxxxxB 1.6 2 2.4 ms Orderable part number TPS36xxxxxxC 9 10 11 ms Orderable part number TPS36xxxxxxD 22.5 25 27.5 ms Orderable part number TPS36xxxxxxE 45 50 55 ms Orderable part number TPS36xxxxxxF 90 100 110 ms Orderable part number TPS36xxxxxxG 180 200 220 ms Orderable part number TPS36xxxxxxH 0.9 1 1.1 s Orderable part number TPS36xxxxxxI 9 10 11 s tWDO Watchdog timeout delay tD s t MR_RES Propagation delay from MR low to reset assertion VDD ≥ VIT– + 0.2 V, MR = V MR_H to V MR_L 100 ns t MR_tD Delay from MR  release to reset deassert VDD = 3.3 V, MR = V MR_L to V MR_H   tD s tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS Specified by design parameter. When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is deasserted after the startup delay (tSTRT) + tD delay. VDD voltage transitions from (VIT– - 10%) to (VIT– + 10%) Timing Diagrams * Added a footnote to for tINIT no Functional Timing Diagram Typical Characteristics all curves are taken at TA = 25°C (unless otherwise noted) VIT- Accuracy vs Temperature VIT- Accuracy Histogram VIT- Hysteresis Vs Temperature Supply Glitch Immunity vs Overdrive Timer Accuracy vs Temperature Timer Accuracy Histogram tWC vs Capacitance tD vs Capacitance RESET VOL vs I sink, VDD = 1.5 V WDO VOL vs I sink, VDD = 1.5 V RESET VOL vs I sink, VDD = 3.3 V WDO VOL vs I sink, VDD = 3.3 V RESET VOH vs I source, VDD = 2.0 V WDO VOH vs I source, VDD = 2.0 V RESET VOH vs I source, VDD = 6.0 V WDO VOH vs I source, VDD = 6.0 V Supply Current vs Power-Supply Voltage Specifications Absolute Maximum Ratings over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1 MIN MAX UNIT Voltage VDD –0.3 6.5 V Voltage CWD, CRST, WD–EN, SETx, WDI,  MR (2),  RESET (Push Pull), WDO (Push Pull) –0.3 VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 V   RESET (Open Drain),  WDO (Open Drain) –0.3 6.5 Current RESET,  WDO pin –20 20 mA Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 Operating ambient temperature, TA –40 125 ℃ Temperature Storage, Tstg –65 150 Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.  The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller As a result of the low dissipated power in this device, it is assumed that TJ = TA. Absolute Maximum Ratings over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1 MIN MAX UNIT Voltage VDD –0.3 6.5 V Voltage CWD, CRST, WD–EN, SETx, WDI,  MR (2),  RESET (Push Pull), WDO (Push Pull) –0.3 VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 V   RESET (Open Drain),  WDO (Open Drain) –0.3 6.5 Current RESET,  WDO pin –20 20 mA Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 Operating ambient temperature, TA –40 125 ℃ Temperature Storage, Tstg –65 150 Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.  The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller As a result of the low dissipated power in this device, it is assumed that TJ = TA. over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1 MIN MAX UNIT Voltage VDD –0.3 6.5 V Voltage CWD, CRST, WD–EN, SETx, WDI,  MR (2),  RESET (Push Pull), WDO (Push Pull) –0.3 VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 V   RESET (Open Drain),  WDO (Open Drain) –0.3 6.5 Current RESET,  WDO pin –20 20 mA Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 Operating ambient temperature, TA –40 125 ℃ Temperature Storage, Tstg –65 150 over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1 MIN MAX UNIT Voltage VDD –0.3 6.5 V Voltage CWD, CRST, WD–EN, SETx, WDI,  MR (2),  RESET (Push Pull), WDO (Push Pull) –0.3 VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 V   RESET (Open Drain),  WDO (Open Drain) –0.3 6.5 Current RESET,  WDO pin –20 20 mA Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 Operating ambient temperature, TA –40 125 ℃ Temperature Storage, Tstg –65 150 MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Voltage VDD –0.3 6.5 V Voltage CWD, CRST, WD–EN, SETx, WDI,  MR (2),  RESET (Push Pull), WDO (Push Pull) –0.3 VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 V   RESET (Open Drain),  WDO (Open Drain) –0.3 6.5 Current RESET,  WDO pin –20 20 mA Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 Operating ambient temperature, TA –40 125 ℃ Temperature Storage, Tstg –65 150 Voltage VDD –0.3 6.5 V VoltageVDD–0.36.5V Voltage CWD, CRST, WD–EN, SETx, WDI,  MR (2),  RESET (Push Pull), WDO (Push Pull) –0.3 VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 V VoltageCWD, CRST, WD–EN, SETx, WDI,  MR (2),  RESET (Push Pull), WDO (Push Pull)WDRSTMR(2)  RESET (Push Pull),RESETWDO–0.3VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1 DD#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1V   RESET (Open Drain),  WDO (Open Drain) –0.3 6.5   RESET (Open Drain),  WDO (Open Drain) RESET (Open Drain), RESET WDO (Open Drain)WDO–0.36.5 Current RESET,  WDO pin –20 20 mA Current RESET,  WDO pin RESET, RESET,WDO–2020mA Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 Operating ambient temperature, TA –40 125 ℃ Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2Operating ambient temperature, TA A–40125℃ Temperature Storage, Tstg –65 150 TemperatureStorage, Tstg stg–65150 Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.  The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller As a result of the low dissipated power in this device, it is assumed that TJ = TA. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating ConditionIf the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. MRDDDDMRThe absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smallerAs a result of the low dissipated power in this device, it is assumed that TJ = TA.JA ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1±2000V Charged device model (CDM), per AEC Q100-011 ±750 Charged device model (CDM), per AEC Q100-011±750 AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Voltage VDD (Active Low output) 0.9 6 V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD RESET (Open Drain) , WDO (Open Drain) 0 6 RESET (Open Drain) , WDO (Push Pull) 0 VDD Current RESET, WDO pin current –5 5 mA CRST CRST pin capacitor range 1.5 1800 nF CWD CWD pin capacitor range 1.5 1000 nF TA Operating ambient temperature –40 125 ℃ If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Voltage VDD (Active Low output) 0.9 6 V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD RESET (Open Drain) , WDO (Open Drain) 0 6 RESET (Open Drain) , WDO (Push Pull) 0 VDD Current RESET, WDO pin current –5 5 mA CRST CRST pin capacitor range 1.5 1800 nF CWD CWD pin capacitor range 1.5 1000 nF TA Operating ambient temperature –40 125 ℃ If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD. over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Voltage VDD (Active Low output) 0.9 6 V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD RESET (Open Drain) , WDO (Open Drain) 0 6 RESET (Open Drain) , WDO (Push Pull) 0 VDD Current RESET, WDO pin current –5 5 mA CRST CRST pin capacitor range 1.5 1800 nF CWD CWD pin capacitor range 1.5 1000 nF TA Operating ambient temperature –40 125 ℃ over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Voltage VDD (Active Low output) 0.9 6 V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD RESET (Open Drain) , WDO (Open Drain) 0 6 RESET (Open Drain) , WDO (Push Pull) 0 VDD Current RESET, WDO pin current –5 5 mA CRST CRST pin capacitor range 1.5 1800 nF CWD CWD pin capacitor range 1.5 1000 nF TA Operating ambient temperature –40 125 ℃ MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT Voltage VDD (Active Low output) 0.9 6 V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD RESET (Open Drain) , WDO (Open Drain) 0 6 RESET (Open Drain) , WDO (Push Pull) 0 VDD Current RESET, WDO pin current –5 5 mA CRST CRST pin capacitor range 1.5 1800 nF CWD CWD pin capacitor range 1.5 1000 nF TA Operating ambient temperature –40 125 ℃ Voltage VDD (Active Low output) 0.9 6 V VoltageVDD (Active Low output)0.96V CWD, CRST, WD–EN, SETx, WDI, MR (1) 0 VDD CWD, CRST, WD–EN, SETx, WDI, MR (1) WDRSTMR(1)0VDD RESET (Open Drain) , WDO (Open Drain) 0 6 RESET (Open Drain) , WDO (Open Drain) RESET RESET (Open Drain) ,WDO06 RESET (Open Drain) , WDO (Push Pull) 0 VDD RESET (Open Drain) , WDO (Push Pull) RESET RESET(Open Drain) ,WDO0VDD Current RESET, WDO pin current –5 5 mA Current RESET, WDO pin current RESET,RESETWDO–55mA CRST CRST pin capacitor range 1.5 1800 nF CRST RSTCRST pin capacitor rangeRST1.51800nF CWD CWD pin capacitor range 1.5 1000 nF CWD WDCWD pin capacitor rangeWD1.51000nF TA Operating ambient temperature –40 125 ℃ TA AOperating ambient temperature–40125℃ If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD. If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD. MRDDDDMRMRDD. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS36-Q1 UNIT DDF (SOT23-8) 8 PINS RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJB Junction-to-board thermal resistance 92.4 °C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJB Junction-to-board characterization parameter 91.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS36-Q1 UNIT DDF (SOT23-8) 8 PINS RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJB Junction-to-board thermal resistance 92.4 °C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJB Junction-to-board characterization parameter 91.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS36-Q1 UNIT DDF (SOT23-8) 8 PINS RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJB Junction-to-board thermal resistance 92.4 °C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJB Junction-to-board characterization parameter 91.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS36-Q1 UNIT DDF (SOT23-8) 8 PINS RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJB Junction-to-board thermal resistance 92.4 °C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJB Junction-to-board characterization parameter 91.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS36-Q1 UNIT DDF (SOT23-8) 8 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS36-Q1 UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1 TPS36-Q1 TPS36-Q1UNIT DDF (SOT23-8) DDF (SOT23-8) 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJB Junction-to-board thermal resistance 92.4 °C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJB Junction-to-board characterization parameter 91.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance 175.3 °C/W RθJA θJAJunction-to-ambient thermal resistance175.3°C/W RθJC(top) Junction-to-case (top) thermal resistance 94.7 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance94.7°C/W RθJB Junction-to-board thermal resistance 92.4 °C/W RθJB θJBJunction-to-board thermal resistance92.4°C/W ψJT Junction-to-top characterization parameter 8.4 °C/W ψJT JTJunction-to-top characterization parameter8.4°C/W ψJB Junction-to-board characterization parameter 91.9 °C/W ψJB JBJunction-to-board characterization parameter91.9°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistanceN/A°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V VIT– Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1_SF1 VIT– = 1.05 V to 1.95 V –1.4 ±0.5 1.4 % VIT– = 2.0 V to 5.4 V –1.2 ±0.5 1.2 VHYS Hysteresis VIT– pin VIT– = 1.05 V to 5.4 V 3 5 7 % IDD Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF1 VDD = 2 VVIT– = 1.05 V to 1.95 V TA = –40℃ to 85℃  0.25 0.8 µA 0.25 3 VDD = 6 VVIT– = 1.05 V to 5.4 V TA = –40℃ to 85℃  0.25 0.8 0.25 3 VIL Low level input voltage WD–EN, WDI, SETx, MR (3) 0.3VDD V VIH High level input voltage WD–EN, WDI, SETx, MR (3) 0.7VDD V R MR Manual reset internal pull-up resistance 100 kΩ RESET / WDO (Open-drain active-low) VOL Low level output voltage  VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA 300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6VTA = –40℃ to 85℃ 10 30 nA VDD = VPULLUP = 6V 10 120 nA RESET / WDO (Push-pull active-low) VPOR Power on RESET voltage (5) VOL(max) = 300 mVIOUT(Sink) = 15 µA 900 mV VOL Low level output voltage  VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA 300 mV VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA 300 VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA 300 VOH High level output voltage  VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA 0.8VDD V VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA 0.8VDD VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mA 0.8VDD VIT– threshold voltage range from 1.05 V to 5.4 V in 50 mV steps. If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VPOR is the minimum VDD voltage level for a controlled output state Electrical Characteristics At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V VIT– Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1_SF1 VIT– = 1.05 V to 1.95 V –1.4 ±0.5 1.4 % VIT– = 2.0 V to 5.4 V –1.2 ±0.5 1.2 VHYS Hysteresis VIT– pin VIT– = 1.05 V to 5.4 V 3 5 7 % IDD Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF1 VDD = 2 VVIT– = 1.05 V to 1.95 V TA = –40℃ to 85℃  0.25 0.8 µA 0.25 3 VDD = 6 VVIT– = 1.05 V to 5.4 V TA = –40℃ to 85℃  0.25 0.8 0.25 3 VIL Low level input voltage WD–EN, WDI, SETx, MR (3) 0.3VDD V VIH High level input voltage WD–EN, WDI, SETx, MR (3) 0.7VDD V R MR Manual reset internal pull-up resistance 100 kΩ RESET / WDO (Open-drain active-low) VOL Low level output voltage  VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA 300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6VTA = –40℃ to 85℃ 10 30 nA VDD = VPULLUP = 6V 10 120 nA RESET / WDO (Push-pull active-low) VPOR Power on RESET voltage (5) VOL(max) = 300 mVIOUT(Sink) = 15 µA 900 mV VOL Low level output voltage  VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA 300 mV VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA 300 VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA 300 VOH High level output voltage  VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA 0.8VDD V VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA 0.8VDD VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mA 0.8VDD VIT– threshold voltage range from 1.05 V to 5.4 V in 50 mV steps. If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VPOR is the minimum VDD voltage level for a controlled output state At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V VIT– Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1_SF1 VIT– = 1.05 V to 1.95 V –1.4 ±0.5 1.4 % VIT– = 2.0 V to 5.4 V –1.2 ±0.5 1.2 VHYS Hysteresis VIT– pin VIT– = 1.05 V to 5.4 V 3 5 7 % IDD Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF1 VDD = 2 VVIT– = 1.05 V to 1.95 V TA = –40℃ to 85℃  0.25 0.8 µA 0.25 3 VDD = 6 VVIT– = 1.05 V to 5.4 V TA = –40℃ to 85℃  0.25 0.8 0.25 3 VIL Low level input voltage WD–EN, WDI, SETx, MR (3) 0.3VDD V VIH High level input voltage WD–EN, WDI, SETx, MR (3) 0.7VDD V R MR Manual reset internal pull-up resistance 100 kΩ RESET / WDO (Open-drain active-low) VOL Low level output voltage  VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA 300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6VTA = –40℃ to 85℃ 10 30 nA VDD = VPULLUP = 6V 10 120 nA RESET / WDO (Push-pull active-low) VPOR Power on RESET voltage (5) VOL(max) = 300 mVIOUT(Sink) = 15 µA 900 mV VOL Low level output voltage  VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA 300 mV VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA 300 VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA 300 VOH High level output voltage  VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA 0.8VDD V VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA 0.8VDD VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mA 0.8VDD At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃DDMR RESETpull-upWDOpull-upLOADA PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V VIT– Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1_SF1 VIT– = 1.05 V to 1.95 V –1.4 ±0.5 1.4 % VIT– = 2.0 V to 5.4 V –1.2 ±0.5 1.2 VHYS Hysteresis VIT– pin VIT– = 1.05 V to 5.4 V 3 5 7 % IDD Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF1 VDD = 2 VVIT– = 1.05 V to 1.95 V TA = –40℃ to 85℃  0.25 0.8 µA 0.25 3 VDD = 6 VVIT– = 1.05 V to 5.4 V TA = –40℃ to 85℃  0.25 0.8 0.25 3 VIL Low level input voltage WD–EN, WDI, SETx, MR (3) 0.3VDD V VIH High level input voltage WD–EN, WDI, SETx, MR (3) 0.7VDD V R MR Manual reset internal pull-up resistance 100 kΩ RESET / WDO (Open-drain active-low) VOL Low level output voltage  VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA 300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6VTA = –40℃ to 85℃ 10 30 nA VDD = VPULLUP = 6V 10 120 nA RESET / WDO (Push-pull active-low) VPOR Power on RESET voltage (5) VOL(max) = 300 mVIOUT(Sink) = 15 µA 900 mV VOL Low level output voltage  VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA 300 mV VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA 300 VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA 300 VOH High level output voltage  VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA 0.8VDD V VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA 0.8VDD VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mA 0.8VDD PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V VIT– Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1_SF1 VIT– = 1.05 V to 1.95 V –1.4 ±0.5 1.4 % VIT– = 2.0 V to 5.4 V –1.2 ±0.5 1.2 VHYS Hysteresis VIT– pin VIT– = 1.05 V to 5.4 V 3 5 7 % IDD Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF1 VDD = 2 VVIT– = 1.05 V to 1.95 V TA = –40℃ to 85℃  0.25 0.8 µA 0.25 3 VDD = 6 VVIT– = 1.05 V to 5.4 V TA = –40℃ to 85℃  0.25 0.8 0.25 3 VIL Low level input voltage WD–EN, WDI, SETx, MR (3) 0.3VDD V VIH High level input voltage WD–EN, WDI, SETx, MR (3) 0.7VDD V R MR Manual reset internal pull-up resistance 100 kΩ RESET / WDO (Open-drain active-low) VOL Low level output voltage  VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA 300 mV VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA 300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6VTA = –40℃ to 85℃ 10 30 nA VDD = VPULLUP = 6V 10 120 nA RESET / WDO (Push-pull active-low) VPOR Power on RESET voltage (5) VOL(max) = 300 mVIOUT(Sink) = 15 µA 900 mV VOL Low level output voltage  VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA 300 mV VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA 300 VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA 300 VOH High level output voltage  VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA 0.8VDD V VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA 0.8VDD VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mA 0.8VDD COMMON PARAMETERS COMMON PARAMETERS VDD Input supply voltage Active LOW output 1.04 6 V VDD DDInput supply voltageActive LOW output1.046V VIT– Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1_SF1 VIT– = 1.05 V to 1.95 V –1.4 ±0.5 1.4 % VIT– IT–Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1_SF1VIT– = 1.05 V to 1.95 VIT––1.4±0.51.4% VIT– = 2.0 V to 5.4 V –1.2 ±0.5 1.2 VIT– = 2.0 V to 5.4 VIT––1.2±0.51.2 VHYS Hysteresis VIT– pin VIT– = 1.05 V to 5.4 V 3 5 7 % VHYS HYSHysteresis VIT– pinIT–VIT– = 1.05 V to 5.4 VIT–357% IDD Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF1 VDD = 2 VVIT– = 1.05 V to 1.95 V TA = –40℃ to 85℃  0.25 0.8 µA IDD DDSupply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244580/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5_SF1VDD = 2 VVIT– = 1.05 V to 1.95 VDDIT–TA = –40℃ to 85℃ A0.250.8µA 0.25 3 0.253 VDD = 6 VVIT– = 1.05 V to 5.4 V TA = –40℃ to 85℃  0.25 0.8 VDD = 6 VVIT– = 1.05 V to 5.4 VDDIT–TA = –40℃ to 85℃ A0.250.8 0.25 3 0.253 VIL Low level input voltage WD–EN, WDI, SETx, MR (3) 0.3VDD V VIL ILLow level input voltage WD–EN, WDI, SETx, MR (3) MR(3)0.3VDD DDV VIH High level input voltage WD–EN, WDI, SETx, MR (3) 0.7VDD V VIH IHHigh level input voltage WD–EN, WDI, SETx, MR (3) MR(3)0.7VDD DDV R MR Manual reset internal pull-up resistance 100 kΩ R MR MR MRManual reset internal pull-up resistance100kΩ RESET / WDO (Open-drain active-low) RESET / WDO (Open-drain active-low)RESETWDO VOL Low level output voltage  VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA 300 mV VOL OLLow level output voltage VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µADDIT–OUT(Sink)300mV VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA 300 VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mADDIT–OUT(Sink)300 Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6VTA = –40℃ to 85℃ 10 30 nA Ilkg(OD) lkg(OD)Open-Drain output leakage currentVDD = VPULLUP = 6VTA = –40℃ to 85℃DDPULLUPA1030nA VDD = VPULLUP = 6V 10 120 nA VDD = VPULLUP = 6VDDPULLUP10120nA RESET / WDO (Push-pull active-low) RESET / WDO (Push-pull active-low)RESETWDO VPOR Power on RESET voltage (5) VOL(max) = 300 mVIOUT(Sink) = 15 µA 900 mV VPOR PORPower on RESET voltage (5) RESET(5)VOL(max) = 300 mVIOUT(Sink) = 15 µAOL(max)OUT(Sink)900mV VOL Low level output voltage  VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA 300 mV VOL OLLow level output voltage VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µADDIT–OUT(Sink)300mV VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA 300 VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µADDIT–OUT(Sink)300 VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA 300 VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mADDIT–OUT(Sink)300 VOH High level output voltage  VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA 0.8VDD V VOH OHHigh level output voltage VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µADD IT–OUT(Source)0.8VDD DDV VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA 0.8VDD VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µADD IT–OUT(Source)0.8VDD DD VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mA 0.8VDD VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mADD IT–OUT(Source)0.8VDD DD VIT– threshold voltage range from 1.05 V to 5.4 V in 50 mV steps. If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VPOR is the minimum VDD voltage level for a controlled output state VIT– threshold voltage range from 1.05 V to 5.4 V in 50 mV steps.IT–If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.MRDDDD MRVPOR is the minimum VDD voltage level for a controlled output statePORDD Timing Requirements At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tGI_VIT– Glitch immunity VIT– 5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2_SF2 15 µs t MR_PW MR pin pulse duration to assert reset 100 ns tP-WD WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 500 ns tHD-WDEN WD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 200 µs tHD-SETx SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 150 µs tWC Watchdog close window time period Orderable Option TPS36xxxxB 0.8 1 1.2 ms Orderable Option TPS36xxxxC 4 5 6 Orderable Option TPS36xxxxD 9 10 11 Orderable Option TPS36xxxxE 18 20 22 Orderable Option TPS36xxxxF 45 50 55 Orderable Option TPS36xxxxG 90 100 110 Orderable Option TPS36xxxxH 180 200 220 Orderable Option TPS36xxxxI 0.9 1 1.1 s Orderable Option TPS36xxxxJ 1.26 1.4 1.54 Orderable Option TPS36xxxxK 1.44 1.6 1.76 Orderable Option TPS36xxxxL 9 10 11 Orderable Option TPS36xxxxM 45 50 55 Orderable Option TPS36xxxxN 90 100 110 tWO Watchdog open window time period SETx pin decide multipler n (n-1) X tWC ms Overdrive % = [(VDD/ VIT–) – 1] × 100% Not production tested Timing Requirements At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tGI_VIT– Glitch immunity VIT– 5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2_SF2 15 µs t MR_PW MR pin pulse duration to assert reset 100 ns tP-WD WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 500 ns tHD-WDEN WD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 200 µs tHD-SETx SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 150 µs tWC Watchdog close window time period Orderable Option TPS36xxxxB 0.8 1 1.2 ms Orderable Option TPS36xxxxC 4 5 6 Orderable Option TPS36xxxxD 9 10 11 Orderable Option TPS36xxxxE 18 20 22 Orderable Option TPS36xxxxF 45 50 55 Orderable Option TPS36xxxxG 90 100 110 Orderable Option TPS36xxxxH 180 200 220 Orderable Option TPS36xxxxI 0.9 1 1.1 s Orderable Option TPS36xxxxJ 1.26 1.4 1.54 Orderable Option TPS36xxxxK 1.44 1.6 1.76 Orderable Option TPS36xxxxL 9 10 11 Orderable Option TPS36xxxxM 45 50 55 Orderable Option TPS36xxxxN 90 100 110 tWO Watchdog open window time period SETx pin decide multipler n (n-1) X tWC ms Overdrive % = [(VDD/ VIT–) – 1] × 100% Not production tested At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tGI_VIT– Glitch immunity VIT– 5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2_SF2 15 µs t MR_PW MR pin pulse duration to assert reset 100 ns tP-WD WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 500 ns tHD-WDEN WD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 200 µs tHD-SETx SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 150 µs tWC Watchdog close window time period Orderable Option TPS36xxxxB 0.8 1 1.2 ms Orderable Option TPS36xxxxC 4 5 6 Orderable Option TPS36xxxxD 9 10 11 Orderable Option TPS36xxxxE 18 20 22 Orderable Option TPS36xxxxF 45 50 55 Orderable Option TPS36xxxxG 90 100 110 Orderable Option TPS36xxxxH 180 200 220 Orderable Option TPS36xxxxI 0.9 1 1.1 s Orderable Option TPS36xxxxJ 1.26 1.4 1.54 Orderable Option TPS36xxxxK 1.44 1.6 1.76 Orderable Option TPS36xxxxL 9 10 11 Orderable Option TPS36xxxxM 45 50 55 Orderable Option TPS36xxxxN 90 100 110 tWO Watchdog open window time period SETx pin decide multipler n (n-1) X tWC ms At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃DDMR RESETpull-upWDOpull-upLOADA PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tGI_VIT– Glitch immunity VIT– 5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2_SF2 15 µs t MR_PW MR pin pulse duration to assert reset 100 ns tP-WD WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 500 ns tHD-WDEN WD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 200 µs tHD-SETx SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 150 µs tWC Watchdog close window time period Orderable Option TPS36xxxxB 0.8 1 1.2 ms Orderable Option TPS36xxxxC 4 5 6 Orderable Option TPS36xxxxD 9 10 11 Orderable Option TPS36xxxxE 18 20 22 Orderable Option TPS36xxxxF 45 50 55 Orderable Option TPS36xxxxG 90 100 110 Orderable Option TPS36xxxxH 180 200 220 Orderable Option TPS36xxxxI 0.9 1 1.1 s Orderable Option TPS36xxxxJ 1.26 1.4 1.54 Orderable Option TPS36xxxxK 1.44 1.6 1.76 Orderable Option TPS36xxxxL 9 10 11 Orderable Option TPS36xxxxM 45 50 55 Orderable Option TPS36xxxxN 90 100 110 tWO Watchdog open window time period SETx pin decide multipler n (n-1) X tWC ms PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT tGI_VIT– Glitch immunity VIT– 5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2_SF2 15 µs t MR_PW MR pin pulse duration to assert reset 100 ns tP-WD WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 500 ns tHD-WDEN WD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 200 µs tHD-SETx SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 150 µs tWC Watchdog close window time period Orderable Option TPS36xxxxB 0.8 1 1.2 ms Orderable Option TPS36xxxxC 4 5 6 Orderable Option TPS36xxxxD 9 10 11 Orderable Option TPS36xxxxE 18 20 22 Orderable Option TPS36xxxxF 45 50 55 Orderable Option TPS36xxxxG 90 100 110 Orderable Option TPS36xxxxH 180 200 220 Orderable Option TPS36xxxxI 0.9 1 1.1 s Orderable Option TPS36xxxxJ 1.26 1.4 1.54 Orderable Option TPS36xxxxK 1.44 1.6 1.76 Orderable Option TPS36xxxxL 9 10 11 Orderable Option TPS36xxxxM 45 50 55 Orderable Option TPS36xxxxN 90 100 110 tWO Watchdog open window time period SETx pin decide multipler n (n-1) X tWC ms tGI_VIT– Glitch immunity VIT– 5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2_SF2 15 µs tGI_VIT– GI_VIT– Glitch immunity VIT– IT– 5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2_SF2 IT–#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2_SF215µs t MR_PW MR pin pulse duration to assert reset 100 ns t MR_PW MR_PWMR MR pin pulse duration to assert resetMR100ns tP-WD WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 500 ns tP-WD P-WDWDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOSVDD > VIT– DDIT–500ns tHD-WDEN WD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 200 µs tHD-WDEN HD-WDENWD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOSVDD > VIT– DDIT–200µs tHD-SETx SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS VDD > VIT– 150 µs tHD-SETx HD-SETxSETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244581/SFSEP1E0POOSVDD > VIT– DDIT–150µs tWC Watchdog close window time period Orderable Option TPS36xxxxB 0.8 1 1.2 ms tWC WCWatchdog close window time periodOrderable Option TPS36xxxxB0.811.2ms Orderable Option TPS36xxxxC 4 5 6 Orderable Option TPS36xxxxC456 Orderable Option TPS36xxxxD 9 10 11 Orderable Option TPS36xxxxD91011 Orderable Option TPS36xxxxE 18 20 22 Orderable Option TPS36xxxxE182022 Orderable Option TPS36xxxxF 45 50 55 Orderable Option TPS36xxxxF455055 Orderable Option TPS36xxxxG 90 100 110 Orderable Option TPS36xxxxG90100110 Orderable Option TPS36xxxxH 180 200 220 Orderable Option TPS36xxxxH180200220 Orderable Option TPS36xxxxI 0.9 1 1.1 s Orderable Option TPS36xxxxI0.911.1s Orderable Option TPS36xxxxJ 1.26 1.4 1.54 Orderable Option TPS36xxxxJ1.261.41.54 Orderable Option TPS36xxxxK 1.44 1.6 1.76 Orderable Option TPS36xxxxK1.441.61.76 Orderable Option TPS36xxxxL 9 10 11 Orderable Option TPS36xxxxL91011 Orderable Option TPS36xxxxM 45 50 55 Orderable Option TPS36xxxxM455055 Orderable Option TPS36xxxxN 90 100 110 Orderable Option TPS36xxxxN90100110 tWO Watchdog open window time period SETx pin decide multipler n (n-1) X tWC ms tWO WOWatchdog open window time periodSETx pin decide multipler n n (n-1) X tWC (n-1)WCms Overdrive % = [(VDD/ VIT–) – 1] × 100% Not production tested Overdrive % = [(VDD/ VIT–) – 1] × 100%DDIT–Not production tested Switching Characteristics At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTRT Startup delay(4)   500 µs tP_HL RESET detect delay for VDD falling below VIT– VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1_SF1 30 50 µs tSD Watchdog startup delay Orderable part number TPS36xA, TPS36xG 0 ms Orderable part number TPS36xB, TPS36xH 180 200 220 Orderable part number TPS36xC, TPS36xI 450 500 550 Orderable part number TPS36xD, TPS36xJ 0.9 1 1.1 s Orderable part number TPS36xE, TPS36xK 4.5 5 5.5 Orderable part number TPS36xF, TPS36xL 9 10 11 tD Reset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1_SF1 Orderable part number TPS36xxxxxxB 1.6 2 2.4 ms Orderable part number TPS36xxxxxxC 9 10 11 ms Orderable part number TPS36xxxxxxD 22.5 25 27.5 ms Orderable part number TPS36xxxxxxE 45 50 55 ms Orderable part number TPS36xxxxxxF 90 100 110 ms Orderable part number TPS36xxxxxxG 180 200 220 ms Orderable part number TPS36xxxxxxH 0.9 1 1.1 s Orderable part number TPS36xxxxxxI 9 10 11 s tWDO Watchdog timeout delay tD s t MR_RES Propagation delay from MR low to reset assertion VDD ≥ VIT– + 0.2 V, MR = V MR_H to V MR_L 100 ns t MR_tD Delay from MR  release to reset deassert VDD = 3.3 V, MR = V MR_L to V MR_H   tD s tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS Specified by design parameter. When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is deasserted after the startup delay (tSTRT) + tD delay. VDD voltage transitions from (VIT– - 10%) to (VIT– + 10%) Switching Characteristics At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTRT Startup delay(4)   500 µs tP_HL RESET detect delay for VDD falling below VIT– VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1_SF1 30 50 µs tSD Watchdog startup delay Orderable part number TPS36xA, TPS36xG 0 ms Orderable part number TPS36xB, TPS36xH 180 200 220 Orderable part number TPS36xC, TPS36xI 450 500 550 Orderable part number TPS36xD, TPS36xJ 0.9 1 1.1 s Orderable part number TPS36xE, TPS36xK 4.5 5 5.5 Orderable part number TPS36xF, TPS36xL 9 10 11 tD Reset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1_SF1 Orderable part number TPS36xxxxxxB 1.6 2 2.4 ms Orderable part number TPS36xxxxxxC 9 10 11 ms Orderable part number TPS36xxxxxxD 22.5 25 27.5 ms Orderable part number TPS36xxxxxxE 45 50 55 ms Orderable part number TPS36xxxxxxF 90 100 110 ms Orderable part number TPS36xxxxxxG 180 200 220 ms Orderable part number TPS36xxxxxxH 0.9 1 1.1 s Orderable part number TPS36xxxxxxI 9 10 11 s tWDO Watchdog timeout delay tD s t MR_RES Propagation delay from MR low to reset assertion VDD ≥ VIT– + 0.2 V, MR = V MR_H to V MR_L 100 ns t MR_tD Delay from MR  release to reset deassert VDD = 3.3 V, MR = V MR_L to V MR_H   tD s tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS Specified by design parameter. When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is deasserted after the startup delay (tSTRT) + tD delay. VDD voltage transitions from (VIT– - 10%) to (VIT– + 10%) At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTRT Startup delay(4)   500 µs tP_HL RESET detect delay for VDD falling below VIT– VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1_SF1 30 50 µs tSD Watchdog startup delay Orderable part number TPS36xA, TPS36xG 0 ms Orderable part number TPS36xB, TPS36xH 180 200 220 Orderable part number TPS36xC, TPS36xI 450 500 550 Orderable part number TPS36xD, TPS36xJ 0.9 1 1.1 s Orderable part number TPS36xE, TPS36xK 4.5 5 5.5 Orderable part number TPS36xF, TPS36xL 9 10 11 tD Reset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1_SF1 Orderable part number TPS36xxxxxxB 1.6 2 2.4 ms Orderable part number TPS36xxxxxxC 9 10 11 ms Orderable part number TPS36xxxxxxD 22.5 25 27.5 ms Orderable part number TPS36xxxxxxE 45 50 55 ms Orderable part number TPS36xxxxxxF 90 100 110 ms Orderable part number TPS36xxxxxxG 180 200 220 ms Orderable part number TPS36xxxxxxH 0.9 1 1.1 s Orderable part number TPS36xxxxxxI 9 10 11 s tWDO Watchdog timeout delay tD s t MR_RES Propagation delay from MR low to reset assertion VDD ≥ VIT– + 0.2 V, MR = V MR_H to V MR_L 100 ns t MR_tD Delay from MR  release to reset deassert VDD = 3.3 V, MR = V MR_L to V MR_H   tD s At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃DDMR RESETpull-upWDOpull-upLOADA PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTRT Startup delay(4)   500 µs tP_HL RESET detect delay for VDD falling below VIT– VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1_SF1 30 50 µs tSD Watchdog startup delay Orderable part number TPS36xA, TPS36xG 0 ms Orderable part number TPS36xB, TPS36xH 180 200 220 Orderable part number TPS36xC, TPS36xI 450 500 550 Orderable part number TPS36xD, TPS36xJ 0.9 1 1.1 s Orderable part number TPS36xE, TPS36xK 4.5 5 5.5 Orderable part number TPS36xF, TPS36xL 9 10 11 tD Reset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1_SF1 Orderable part number TPS36xxxxxxB 1.6 2 2.4 ms Orderable part number TPS36xxxxxxC 9 10 11 ms Orderable part number TPS36xxxxxxD 22.5 25 27.5 ms Orderable part number TPS36xxxxxxE 45 50 55 ms Orderable part number TPS36xxxxxxF 90 100 110 ms Orderable part number TPS36xxxxxxG 180 200 220 ms Orderable part number TPS36xxxxxxH 0.9 1 1.1 s Orderable part number TPS36xxxxxxI 9 10 11 s tWDO Watchdog timeout delay tD s t MR_RES Propagation delay from MR low to reset assertion VDD ≥ VIT– + 0.2 V, MR = V MR_H to V MR_L 100 ns t MR_tD Delay from MR  release to reset deassert VDD = 3.3 V, MR = V MR_L to V MR_H   tD s PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT tSTRT Startup delay(4)   500 µs tP_HL RESET detect delay for VDD falling below VIT– VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1_SF1 30 50 µs tSD Watchdog startup delay Orderable part number TPS36xA, TPS36xG 0 ms Orderable part number TPS36xB, TPS36xH 180 200 220 Orderable part number TPS36xC, TPS36xI 450 500 550 Orderable part number TPS36xD, TPS36xJ 0.9 1 1.1 s Orderable part number TPS36xE, TPS36xK 4.5 5 5.5 Orderable part number TPS36xF, TPS36xL 9 10 11 tD Reset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1_SF1 Orderable part number TPS36xxxxxxB 1.6 2 2.4 ms Orderable part number TPS36xxxxxxC 9 10 11 ms Orderable part number TPS36xxxxxxD 22.5 25 27.5 ms Orderable part number TPS36xxxxxxE 45 50 55 ms Orderable part number TPS36xxxxxxF 90 100 110 ms Orderable part number TPS36xxxxxxG 180 200 220 ms Orderable part number TPS36xxxxxxH 0.9 1 1.1 s Orderable part number TPS36xxxxxxI 9 10 11 s tWDO Watchdog timeout delay tD s t MR_RES Propagation delay from MR low to reset assertion VDD ≥ VIT– + 0.2 V, MR = V MR_H to V MR_L 100 ns t MR_tD Delay from MR  release to reset deassert VDD = 3.3 V, MR = V MR_L to V MR_H   tD s tSTRT Startup delay(4)   500 µs tSTRT STRTStartup delay(4) (4)  500µs tP_HL RESET detect delay for VDD falling below VIT– VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1_SF1 30 50 µs tP_HL P_HLRESET detect delay for VDD falling below VIT– IT–VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1_SF1 DD IT+ IT–#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1_SF13050µs tSD Watchdog startup delay Orderable part number TPS36xA, TPS36xG 0 ms tSD SDWatchdog startup delayOrderable part number TPS36xA, TPS36xG0ms Orderable part number TPS36xB, TPS36xH 180 200 220 Orderable part number TPS36xB, TPS36xH180200220 Orderable part number TPS36xC, TPS36xI 450 500 550 Orderable part number TPS36xC, TPS36xI450500550 Orderable part number TPS36xD, TPS36xJ 0.9 1 1.1 s Orderable part number TPS36xD, TPS36xJ0.911.1s Orderable part number TPS36xE, TPS36xK 4.5 5 5.5 Orderable part number TPS36xE, TPS36xK4.555.5 Orderable part number TPS36xF, TPS36xL 9 10 11 Orderable part number TPS36xF, TPS36xL91011 tD Reset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1_SF1 Orderable part number TPS36xxxxxxB 1.6 2 2.4 ms tD DReset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244582/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1_SF1Orderable part number TPS36xxxxxxB1.622.4ms Orderable part number TPS36xxxxxxC 9 10 11 ms Orderable part number TPS36xxxxxxC91011ms Orderable part number TPS36xxxxxxD 22.5 25 27.5 ms Orderable part number TPS36xxxxxxD22.52527.5ms Orderable part number TPS36xxxxxxE 45 50 55 ms Orderable part number TPS36xxxxxxE455055ms Orderable part number TPS36xxxxxxF 90 100 110 ms Orderable part number TPS36xxxxxxF90100110ms Orderable part number TPS36xxxxxxG 180 200 220 ms Orderable part number TPS36xxxxxxG180200220ms Orderable part number TPS36xxxxxxH 0.9 1 1.1 s Orderable part number TPS36xxxxxxH0.911.1s Orderable part number TPS36xxxxxxI 9 10 11 s Orderable part number TPS36xxxxxxI91011s tWDO Watchdog timeout delay tD s tWDO WDOWatchdog timeout delaytD Ds t MR_RES Propagation delay from MR low to reset assertion VDD ≥ VIT– + 0.2 V, MR = V MR_H to V MR_L 100 ns t MR_RES MR_RESMRPropagation delay from MR low to reset assertionMRVDD ≥ VIT– + 0.2 V, MR = V MR_H to V MR_L DDIT–MR MR_H MR MR_LMR100ns t MR_tD Delay from MR  release to reset deassert VDD = 3.3 V, MR = V MR_L to V MR_H   tD s t MR_tD MR_tDMRDelay from MR  release to reset deassertMR VDD = 3.3 V, MR = V MR_L to V MR_H   DDMR MR_L MR MR_H  MRtD Ds tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS Specified by design parameter. When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is deasserted after the startup delay (tSTRT) + tD delay. VDD voltage transitions from (VIT– - 10%) to (VIT– + 10%) tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS P_HLIT–IT+IT–HYSSpecified by design parameter. When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is deasserted after the startup delay (tSTRT) + tD delay.DDIT+STRTDVDD voltage transitions from (VIT– - 10%) to (VIT– + 10%)IT– IT– Timing Diagrams * Added a footnote to for tINIT no Functional Timing Diagram Timing Diagrams * Added a footnote to for tINIT no * Added a footnote to for tINIT no * Added a footnote to for tINIT no *Added a footnote to for tINIT INITno Functional Timing Diagram Functional Timing Diagram Functional Timing Diagram Functional Timing Diagram Typical Characteristics all curves are taken at TA = 25°C (unless otherwise noted) VIT- Accuracy vs Temperature VIT- Accuracy Histogram VIT- Hysteresis Vs Temperature Supply Glitch Immunity vs Overdrive Timer Accuracy vs Temperature Timer Accuracy Histogram tWC vs Capacitance tD vs Capacitance RESET VOL vs I sink, VDD = 1.5 V WDO VOL vs I sink, VDD = 1.5 V RESET VOL vs I sink, VDD = 3.3 V WDO VOL vs I sink, VDD = 3.3 V RESET VOH vs I source, VDD = 2.0 V WDO VOH vs I source, VDD = 2.0 V RESET VOH vs I source, VDD = 6.0 V WDO VOH vs I source, VDD = 6.0 V Supply Current vs Power-Supply Voltage Typical Characteristics all curves are taken at TA = 25°C (unless otherwise noted) VIT- Accuracy vs Temperature VIT- Accuracy Histogram VIT- Hysteresis Vs Temperature Supply Glitch Immunity vs Overdrive Timer Accuracy vs Temperature Timer Accuracy Histogram tWC vs Capacitance tD vs Capacitance RESET VOL vs I sink, VDD = 1.5 V WDO VOL vs I sink, VDD = 1.5 V RESET VOL vs I sink, VDD = 3.3 V WDO VOL vs I sink, VDD = 3.3 V RESET VOH vs I source, VDD = 2.0 V WDO VOH vs I source, VDD = 2.0 V RESET VOH vs I source, VDD = 6.0 V WDO VOH vs I source, VDD = 6.0 V Supply Current vs Power-Supply Voltage all curves are taken at TA = 25°C (unless otherwise noted) VIT- Accuracy vs Temperature VIT- Accuracy Histogram VIT- Hysteresis Vs Temperature Supply Glitch Immunity vs Overdrive Timer Accuracy vs Temperature Timer Accuracy Histogram tWC vs Capacitance tD vs Capacitance RESET VOL vs I sink, VDD = 1.5 V WDO VOL vs I sink, VDD = 1.5 V RESET VOL vs I sink, VDD = 3.3 V WDO VOL vs I sink, VDD = 3.3 V RESET VOH vs I source, VDD = 2.0 V WDO VOH vs I source, VDD = 2.0 V RESET VOH vs I source, VDD = 6.0 V WDO VOH vs I source, VDD = 6.0 V Supply Current vs Power-Supply Voltage all curves are taken at TA = 25°C (unless otherwise noted)A VIT- Accuracy vs Temperature VIT- Accuracy Histogram VIT- Hysteresis Vs Temperature Supply Glitch Immunity vs Overdrive Timer Accuracy vs Temperature Timer Accuracy Histogram tWC vs Capacitance tD vs Capacitance RESET VOL vs I sink, VDD = 1.5 V WDO VOL vs I sink, VDD = 1.5 V RESET VOL vs I sink, VDD = 3.3 V WDO VOL vs I sink, VDD = 3.3 V RESET VOH vs I source, VDD = 2.0 V WDO VOH vs I source, VDD = 2.0 V RESET VOH vs I source, VDD = 6.0 V WDO VOH vs I source, VDD = 6.0 V Supply Current vs Power-Supply Voltage VIT- Accuracy vs Temperature VIT- Accuracy vs TemperatureIT- VIT- Accuracy Histogram VIT- Accuracy HistogramIT- VIT- Hysteresis Vs Temperature VIT- Hysteresis Vs TemperatureIT- Supply Glitch Immunity vs Overdrive Supply Glitch Immunity vs Overdrive Timer Accuracy vs Temperature Timer Accuracy vs Temperature Timer Accuracy Histogram Timer Accuracy Histogram tWC vs Capacitance tWC vs CapacitanceWC tD vs Capacitance tD vs CapacitanceD RESET VOL vs I sink, VDD = 1.5 V RESET VOL vs I sink, VDD = 1.5 VOLsinkDD WDO VOL vs I sink, VDD = 1.5 V WDO VOL vs I sink, VDD = 1.5 VOLsinkDD RESET VOL vs I sink, VDD = 3.3 V RESET VOL vs I sink, VDD = 3.3 VOLsinkDD WDO VOL vs I sink, VDD = 3.3 V WDO VOL vs I sink, VDD = 3.3 VOLsinkDD RESET VOH vs I source, VDD = 2.0 V RESET VOH vs I source, VDD = 2.0 VOHsourceDD WDO VOH vs I source, VDD = 2.0 V WDO VOH vs I source, VDD = 2.0 VOHsourceDD RESET VOH vs I source, VDD = 6.0 V RESET VOH vs I source, VDD = 6.0 VOHsourceDD WDO VOH vs I source, VDD = 6.0 V WDO VOH vs I source, VDD = 6.0 VOHsourceDD Supply Current vs Power-Supply Voltage Supply Current vs Power-Supply Voltage Detailed Description Overview The TPS36-Q1 is a high-accuracy under voltage supervisor with an integrated window watchdog timer device. The device family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are available in 4 different pinout configurations. Each pinout offers access to different features to meet the various application requirements. The device family is rated for -Q100 applications. Functional Block Diagrams Pinout Option A Pinout Option B Pinout Option C Pinout Option D Feature Description Voltage Supervisor The TPS36-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage supervisor function is always active. After the device powers up from VDD < VPOR, the RESET and WDO outputs will be actively driven when VDD is greater than VPOR. The device starts monitoring the supply level when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for tSTRT + tD time after the VDD > VIT+ (VIT- + VHYS). Refer for the tD value computation. For a capacitor based tD delay option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open. Device pinout options A to C offer only RESET output. In these devices the internal RESET output from supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output. The supervisor offers wide range of fixed monitoring thresholds (VIT-) from 1.05 V to 5.40 V in steps of 50 mV. The device asserts the RESET output when the VDD signal falls below VIT- threshold. The device offers hysteresis functionality for voltage supervision. This ensures the supply has recovered above the monitoring threshold before the RESET output is deasserted. The TPS36-Q1 typical voltage hysteresis (VHYS) is 5%. Along with the voltage hysteresis, the device keeps the RESET output asserted for time duration tD after the supply has risen above VIT+. The RESET output assert duration changes from tD to tSTRT + tD if the VDD signal is ramping from voltage < VPOR. The tD time duration can be programmable using an external capacitor or fixed time options offered by the device. The typical timing behavior for a voltage supervisor and the RESET output is showcased in . The voltage supervisor monitoring output has higher priority over watchdog functionality. If the device voltage supervisor output is asserted, the watchdog functionality will be disabled including WDO assert control. The device resumes watchdog related functionality only after the supply is stable and the tD time duration has elapsed. Voltage Supervisor Timing Diagram Window Watchdog Timer The TPS36-Q1 offers high precision window watchdog timer monitoring. The device is available in multiple pinout options A to D which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs. The window watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled. TPS36-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer section for additional details. The window watchdog timer frame consists of two windows namely close window (tWC) followed by open window (tWO). The device monitors the WDI pin for falling edge. User is expected to provide a valid falling edge on WDI pin in the open window. Refer to arrive at the relevant close window and open window values needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWO time duration. An early fault is reported if a WDI falling edge is detected in close window. A late fault is reported if WDI falling edge is not detected in both close and open window. The device asserts RESET output for pinout options A, B and C or WDO output for pinout D for time tD in event of watchdog fault. Refer to arrive at the relevant tD value needed for application. shows the basic operation for window watchdog timer operation. The TPS36-Q1 watchdog functionality supports multiple features. Details are available in following sub sections. Window Watchdog Timer Operation tWC (Close Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The tWC timer for TPS36-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS36-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec. The TPS36-Q1 when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS36-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB to #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVB highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. tWC Equation 1 SET Pin (Pin Configuration A) SET pin value Equation 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN = 1 (Pin Configuration C, D) SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 tWC (sec) = 79.2 x 106 x CCWD (F) 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B) SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) The TPS36-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS36-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer to identify mapping of orderable part number to tWC value. tWO (Open Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition. Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault condition is detected the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the relationship between tWO and tWC. Refer to select available ratio options. tWO = (n - 1) x tWC Each orderable can offer up to 3 ratio options based on the available SET pins. Refer to identify mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC and ratio combination does not lead to tWO value greater than 640 second. Watchdog Enable Disable Operation The TPS36-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below. Disable watchdog during firmware update to avoid host RESET. Disable watchdog during software step-by-step debug operation. Disable watchdog when performing critical task to avoid watchdog error interrupt. Keep watchdog disabled until host boots up. The TPS36-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration C,D) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two methods is available for the user to disable watchdog operation. For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The diagram shows timing behavior with WD-EN pin control. Watchdog Enable: WD-EN Pin Control SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during watchdog operation. Refer section for additional details regarding SET[1:0] pin behavior. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle or device recovery after UV fault, MR low event is needed to detect change in capacitance. Ongoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled. For a pinout with only RESET output, the RESET can assert if supply supervisor error occurs. When enabled the device immediately enters tWC frame and start watchdog monitoring operation. tSD Watchdog Start Up Delay The TPS36-Q1 supports watchdog startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO or RESET assert events during boot. The tSD time is predetermined based on the device part number selected. Refer section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options. The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin. For devices with only RESET output, the RESET pin is asserted. The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin or WDI float functionality as described in section. shows the operation for tSD time frame. tSD Frame Behavior SET Pin Behavior The TPS36-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep. Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated. For a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec. tWO Values with SET0 Pin Only (Pin Configuration A) Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec Pinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin. tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B) Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec Example for Watchdog Close Time setting = 100 msec. Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec. to show the timing behavior with respect to SETx status changes. Watchdog Behavior with SETx Pin Status Watchdog Operation with 2 SET Pins Watchdog Operation with 1 SET Pin Manual RESET The TPS36-Q1 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than 0.3 x VDD, asserts the RESET output. The MR pin has 100 kΩ pull up to VDD. The MR pin can be left floating. The internal pull up will ensure the output is not asserted due to MR pin trigger. The output is deasserted after MR pin voltage rises above 0.7 x VDD voltage and time tD is elapsed. Refer for more details. MR Pin Response RESET and WDO Output The TPS36-Q1 device can offer RESET or RESET with independent WDO output pin. The output configuration is dependent on the pinout variant selected. For a pinout which has only RESET output, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold or watchdog timer error is detected. For a pinout which has independent RESET and WDO output pins, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold. WDO output is asserted only when watchdog timer error is detected. RESET error has higher priority than WDO error. If RESET is asserted when WDO is asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin is deasserted and startup delay frame is terminated. The output will be asserted for tD time when any relevant events described above are detected. The time tD can be programmed by connecting a capacitor between CRST pin and GND or device will assert tD for fixed time duration as selected by orderable part number. Refer section for all available options. describes the relationship between capacitor value and the time tD . Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. t D (sec) = 4.95 x 106 x CCRST (F) TPS36-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to voltage supervisor undervoltage detection, the output latch will be released when VDD voltage rises above the VIT- + VHYS level. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. shows timing behavior of the device with latched output configuration. Output Latch Timing Behavior Device Functional Modes #GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/A_1467996961_SHEET1 summarizes the functional modes of the TPS36-Q1. Device Functional Modes VDD WATCHDOG STATUS WDI WDO RESET VDD < VPOR Not Applicable — Undefined Undefined VPOR ≤ VDD < VIT- Not Applicable Ignored High Low VDD ≥ VIT+ Disabled Ignored High High Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High High Enabled tWC(max) > tpulse 1 Low High Enabled tWC(max) + tWO(max) < tpulse 1 Low High Where tpulse is the time between falling edges on WDI. Detailed Description Overview The TPS36-Q1 is a high-accuracy under voltage supervisor with an integrated window watchdog timer device. The device family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are available in 4 different pinout configurations. Each pinout offers access to different features to meet the various application requirements. The device family is rated for -Q100 applications. Overview The TPS36-Q1 is a high-accuracy under voltage supervisor with an integrated window watchdog timer device. The device family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are available in 4 different pinout configurations. Each pinout offers access to different features to meet the various application requirements. The device family is rated for -Q100 applications. The TPS36-Q1 is a high-accuracy under voltage supervisor with an integrated window watchdog timer device. The device family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are available in 4 different pinout configurations. Each pinout offers access to different features to meet the various application requirements. The device family is rated for -Q100 applications. The TPS36-Q1 is a high-accuracy under voltage supervisor with an integrated window watchdog timer device. The device family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are available in 4 different pinout configurations. Each pinout offers access to different features to meet the various application requirements. The device family is rated for -Q100 applications. TPS36-Q1under voltage supervisor with an integrated window 4The device family is rated for -Q100 applications. Functional Block Diagrams Pinout Option A Pinout Option B Pinout Option C Pinout Option D Functional Block Diagrams Pinout Option A Pinout Option B Pinout Option C Pinout Option D Pinout Option A Pinout Option B Pinout Option C Pinout Option D Pinout Option A Pinout Option A Pinout Option B Pinout Option B Pinout Option C Pinout Option C Pinout Option D Pinout Option D Feature Description Voltage Supervisor The TPS36-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage supervisor function is always active. After the device powers up from VDD < VPOR, the RESET and WDO outputs will be actively driven when VDD is greater than VPOR. The device starts monitoring the supply level when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for tSTRT + tD time after the VDD > VIT+ (VIT- + VHYS). Refer for the tD value computation. For a capacitor based tD delay option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open. Device pinout options A to C offer only RESET output. In these devices the internal RESET output from supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output. The supervisor offers wide range of fixed monitoring thresholds (VIT-) from 1.05 V to 5.40 V in steps of 50 mV. The device asserts the RESET output when the VDD signal falls below VIT- threshold. The device offers hysteresis functionality for voltage supervision. This ensures the supply has recovered above the monitoring threshold before the RESET output is deasserted. The TPS36-Q1 typical voltage hysteresis (VHYS) is 5%. Along with the voltage hysteresis, the device keeps the RESET output asserted for time duration tD after the supply has risen above VIT+. The RESET output assert duration changes from tD to tSTRT + tD if the VDD signal is ramping from voltage < VPOR. The tD time duration can be programmable using an external capacitor or fixed time options offered by the device. The typical timing behavior for a voltage supervisor and the RESET output is showcased in . The voltage supervisor monitoring output has higher priority over watchdog functionality. If the device voltage supervisor output is asserted, the watchdog functionality will be disabled including WDO assert control. The device resumes watchdog related functionality only after the supply is stable and the tD time duration has elapsed. Voltage Supervisor Timing Diagram Window Watchdog Timer The TPS36-Q1 offers high precision window watchdog timer monitoring. The device is available in multiple pinout options A to D which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs. The window watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled. TPS36-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer section for additional details. The window watchdog timer frame consists of two windows namely close window (tWC) followed by open window (tWO). The device monitors the WDI pin for falling edge. User is expected to provide a valid falling edge on WDI pin in the open window. Refer to arrive at the relevant close window and open window values needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWO time duration. An early fault is reported if a WDI falling edge is detected in close window. A late fault is reported if WDI falling edge is not detected in both close and open window. The device asserts RESET output for pinout options A, B and C or WDO output for pinout D for time tD in event of watchdog fault. Refer to arrive at the relevant tD value needed for application. shows the basic operation for window watchdog timer operation. The TPS36-Q1 watchdog functionality supports multiple features. Details are available in following sub sections. Window Watchdog Timer Operation tWC (Close Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The tWC timer for TPS36-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS36-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec. The TPS36-Q1 when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS36-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB to #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVB highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. tWC Equation 1 SET Pin (Pin Configuration A) SET pin value Equation 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN = 1 (Pin Configuration C, D) SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 tWC (sec) = 79.2 x 106 x CCWD (F) 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B) SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) The TPS36-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS36-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer to identify mapping of orderable part number to tWC value. tWO (Open Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition. Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault condition is detected the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the relationship between tWO and tWC. Refer to select available ratio options. tWO = (n - 1) x tWC Each orderable can offer up to 3 ratio options based on the available SET pins. Refer to identify mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC and ratio combination does not lead to tWO value greater than 640 second. Watchdog Enable Disable Operation The TPS36-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below. Disable watchdog during firmware update to avoid host RESET. Disable watchdog during software step-by-step debug operation. Disable watchdog when performing critical task to avoid watchdog error interrupt. Keep watchdog disabled until host boots up. The TPS36-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration C,D) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two methods is available for the user to disable watchdog operation. For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The diagram shows timing behavior with WD-EN pin control. Watchdog Enable: WD-EN Pin Control SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during watchdog operation. Refer section for additional details regarding SET[1:0] pin behavior. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle or device recovery after UV fault, MR low event is needed to detect change in capacitance. Ongoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled. For a pinout with only RESET output, the RESET can assert if supply supervisor error occurs. When enabled the device immediately enters tWC frame and start watchdog monitoring operation. tSD Watchdog Start Up Delay The TPS36-Q1 supports watchdog startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO or RESET assert events during boot. The tSD time is predetermined based on the device part number selected. Refer section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options. The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin. For devices with only RESET output, the RESET pin is asserted. The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin or WDI float functionality as described in section. shows the operation for tSD time frame. tSD Frame Behavior SET Pin Behavior The TPS36-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep. Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated. For a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec. tWO Values with SET0 Pin Only (Pin Configuration A) Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec Pinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin. tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B) Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec Example for Watchdog Close Time setting = 100 msec. Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec. to show the timing behavior with respect to SETx status changes. Watchdog Behavior with SETx Pin Status Watchdog Operation with 2 SET Pins Watchdog Operation with 1 SET Pin Manual RESET The TPS36-Q1 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than 0.3 x VDD, asserts the RESET output. The MR pin has 100 kΩ pull up to VDD. The MR pin can be left floating. The internal pull up will ensure the output is not asserted due to MR pin trigger. The output is deasserted after MR pin voltage rises above 0.7 x VDD voltage and time tD is elapsed. Refer for more details. MR Pin Response RESET and WDO Output The TPS36-Q1 device can offer RESET or RESET with independent WDO output pin. The output configuration is dependent on the pinout variant selected. For a pinout which has only RESET output, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold or watchdog timer error is detected. For a pinout which has independent RESET and WDO output pins, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold. WDO output is asserted only when watchdog timer error is detected. RESET error has higher priority than WDO error. If RESET is asserted when WDO is asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin is deasserted and startup delay frame is terminated. The output will be asserted for tD time when any relevant events described above are detected. The time tD can be programmed by connecting a capacitor between CRST pin and GND or device will assert tD for fixed time duration as selected by orderable part number. Refer section for all available options. describes the relationship between capacitor value and the time tD . Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. t D (sec) = 4.95 x 106 x CCRST (F) TPS36-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to voltage supervisor undervoltage detection, the output latch will be released when VDD voltage rises above the VIT- + VHYS level. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. shows timing behavior of the device with latched output configuration. Output Latch Timing Behavior Feature Description Voltage Supervisor The TPS36-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage supervisor function is always active. After the device powers up from VDD < VPOR, the RESET and WDO outputs will be actively driven when VDD is greater than VPOR. The device starts monitoring the supply level when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for tSTRT + tD time after the VDD > VIT+ (VIT- + VHYS). Refer for the tD value computation. For a capacitor based tD delay option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open. Device pinout options A to C offer only RESET output. In these devices the internal RESET output from supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output. The supervisor offers wide range of fixed monitoring thresholds (VIT-) from 1.05 V to 5.40 V in steps of 50 mV. The device asserts the RESET output when the VDD signal falls below VIT- threshold. The device offers hysteresis functionality for voltage supervision. This ensures the supply has recovered above the monitoring threshold before the RESET output is deasserted. The TPS36-Q1 typical voltage hysteresis (VHYS) is 5%. Along with the voltage hysteresis, the device keeps the RESET output asserted for time duration tD after the supply has risen above VIT+. The RESET output assert duration changes from tD to tSTRT + tD if the VDD signal is ramping from voltage < VPOR. The tD time duration can be programmable using an external capacitor or fixed time options offered by the device. The typical timing behavior for a voltage supervisor and the RESET output is showcased in . The voltage supervisor monitoring output has higher priority over watchdog functionality. If the device voltage supervisor output is asserted, the watchdog functionality will be disabled including WDO assert control. The device resumes watchdog related functionality only after the supply is stable and the tD time duration has elapsed. Voltage Supervisor Timing Diagram Voltage Supervisor The TPS36-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage supervisor function is always active. After the device powers up from VDD < VPOR, the RESET and WDO outputs will be actively driven when VDD is greater than VPOR. The device starts monitoring the supply level when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for tSTRT + tD time after the VDD > VIT+ (VIT- + VHYS). Refer for the tD value computation. For a capacitor based tD delay option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open. Device pinout options A to C offer only RESET output. In these devices the internal RESET output from supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output. The supervisor offers wide range of fixed monitoring thresholds (VIT-) from 1.05 V to 5.40 V in steps of 50 mV. The device asserts the RESET output when the VDD signal falls below VIT- threshold. The device offers hysteresis functionality for voltage supervision. This ensures the supply has recovered above the monitoring threshold before the RESET output is deasserted. The TPS36-Q1 typical voltage hysteresis (VHYS) is 5%. Along with the voltage hysteresis, the device keeps the RESET output asserted for time duration tD after the supply has risen above VIT+. The RESET output assert duration changes from tD to tSTRT + tD if the VDD signal is ramping from voltage < VPOR. The tD time duration can be programmable using an external capacitor or fixed time options offered by the device. The typical timing behavior for a voltage supervisor and the RESET output is showcased in . The voltage supervisor monitoring output has higher priority over watchdog functionality. If the device voltage supervisor output is asserted, the watchdog functionality will be disabled including WDO assert control. The device resumes watchdog related functionality only after the supply is stable and the tD time duration has elapsed. Voltage Supervisor Timing Diagram The TPS36-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage supervisor function is always active. After the device powers up from VDD < VPOR, the RESET and WDO outputs will be actively driven when VDD is greater than VPOR. The device starts monitoring the supply level when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for tSTRT + tD time after the VDD > VIT+ (VIT- + VHYS). Refer for the tD value computation. For a capacitor based tD delay option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open. Device pinout options A to C offer only RESET output. In these devices the internal RESET output from supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output. The supervisor offers wide range of fixed monitoring thresholds (VIT-) from 1.05 V to 5.40 V in steps of 50 mV. The device asserts the RESET output when the VDD signal falls below VIT- threshold. The device offers hysteresis functionality for voltage supervision. This ensures the supply has recovered above the monitoring threshold before the RESET output is deasserted. The TPS36-Q1 typical voltage hysteresis (VHYS) is 5%. Along with the voltage hysteresis, the device keeps the RESET output asserted for time duration tD after the supply has risen above VIT+. The RESET output assert duration changes from tD to tSTRT + tD if the VDD signal is ramping from voltage < VPOR. The tD time duration can be programmable using an external capacitor or fixed time options offered by the device. The typical timing behavior for a voltage supervisor and the RESET output is showcased in . The voltage supervisor monitoring output has higher priority over watchdog functionality. If the device voltage supervisor output is asserted, the watchdog functionality will be disabled including WDO assert control. The device resumes watchdog related functionality only after the supply is stable and the tD time duration has elapsed. Voltage Supervisor Timing Diagram The TPS36-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage supervisor function is always active. After the device powers up from VDD < VPOR, the RESET and WDO outputs will be actively driven when VDD is greater than VPOR. The device starts monitoring the supply level when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for tSTRT + tD time after the VDD > VIT+ (VIT- + VHYS). Refer for the tD value computation. For a capacitor based tD delay option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open. TPS36-Q1PORPORSTRTDIT+IT-HYS DDSTRTDevice pinout options A to C offer only RESET output. In these devices the internal RESET output from supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output.The supervisor offers wide range of fixed monitoring thresholds (VIT-) from 1.05 V to 5.40 V in steps of 50 mV. The device asserts the RESET output when the VDD signal falls below VIT- threshold. The device offers hysteresis functionality for voltage supervision. This ensures the supply has recovered above the monitoring threshold before the RESET output is deasserted. The TPS36-Q1 typical voltage hysteresis (VHYS) is 5%. Along with the voltage hysteresis, the device keeps the RESET output asserted for time duration tD after the supply has risen above VIT+. The RESET output assert duration changes from tD to tSTRT + tD if the VDD signal is ramping from voltage < VPOR. The tD time duration can be programmable using an external capacitor or fixed time options offered by the device.IT-IT-TPS36-Q1HYSDIT+DSTRTDPORDThe typical timing behavior for a voltage supervisor and the RESET output is showcased in . The voltage supervisor monitoring output has higher priority over watchdog functionality. If the device voltage supervisor output is asserted, the watchdog functionality will be disabled including WDO assert control. The device resumes watchdog related functionality only after the supply is stable and the tD time duration has elapsed.D Voltage Supervisor Timing Diagram Voltage Supervisor Timing Diagram Window Watchdog Timer The TPS36-Q1 offers high precision window watchdog timer monitoring. The device is available in multiple pinout options A to D which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs. The window watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled. TPS36-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer section for additional details. The window watchdog timer frame consists of two windows namely close window (tWC) followed by open window (tWO). The device monitors the WDI pin for falling edge. User is expected to provide a valid falling edge on WDI pin in the open window. Refer to arrive at the relevant close window and open window values needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWO time duration. An early fault is reported if a WDI falling edge is detected in close window. A late fault is reported if WDI falling edge is not detected in both close and open window. The device asserts RESET output for pinout options A, B and C or WDO output for pinout D for time tD in event of watchdog fault. Refer to arrive at the relevant tD value needed for application. shows the basic operation for window watchdog timer operation. The TPS36-Q1 watchdog functionality supports multiple features. Details are available in following sub sections. Window Watchdog Timer Operation tWC (Close Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The tWC timer for TPS36-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS36-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec. The TPS36-Q1 when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS36-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB to #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVB highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. tWC Equation 1 SET Pin (Pin Configuration A) SET pin value Equation 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN = 1 (Pin Configuration C, D) SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 tWC (sec) = 79.2 x 106 x CCWD (F) 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B) SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) The TPS36-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS36-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer to identify mapping of orderable part number to tWC value. tWO (Open Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition. Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault condition is detected the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the relationship between tWO and tWC. Refer to select available ratio options. tWO = (n - 1) x tWC Each orderable can offer up to 3 ratio options based on the available SET pins. Refer to identify mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC and ratio combination does not lead to tWO value greater than 640 second. Watchdog Enable Disable Operation The TPS36-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below. Disable watchdog during firmware update to avoid host RESET. Disable watchdog during software step-by-step debug operation. Disable watchdog when performing critical task to avoid watchdog error interrupt. Keep watchdog disabled until host boots up. The TPS36-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration C,D) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two methods is available for the user to disable watchdog operation. For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The diagram shows timing behavior with WD-EN pin control. Watchdog Enable: WD-EN Pin Control SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during watchdog operation. Refer section for additional details regarding SET[1:0] pin behavior. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle or device recovery after UV fault, MR low event is needed to detect change in capacitance. Ongoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled. For a pinout with only RESET output, the RESET can assert if supply supervisor error occurs. When enabled the device immediately enters tWC frame and start watchdog monitoring operation. tSD Watchdog Start Up Delay The TPS36-Q1 supports watchdog startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO or RESET assert events during boot. The tSD time is predetermined based on the device part number selected. Refer section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options. The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin. For devices with only RESET output, the RESET pin is asserted. The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin or WDI float functionality as described in section. shows the operation for tSD time frame. tSD Frame Behavior SET Pin Behavior The TPS36-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep. Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated. For a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec. tWO Values with SET0 Pin Only (Pin Configuration A) Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec Pinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin. tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B) Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec Example for Watchdog Close Time setting = 100 msec. Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec. to show the timing behavior with respect to SETx status changes. Watchdog Behavior with SETx Pin Status Watchdog Operation with 2 SET Pins Watchdog Operation with 1 SET Pin Window Watchdog Timer The TPS36-Q1 offers high precision window watchdog timer monitoring. The device is available in multiple pinout options A to D which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs. The window watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled. TPS36-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer section for additional details. The window watchdog timer frame consists of two windows namely close window (tWC) followed by open window (tWO). The device monitors the WDI pin for falling edge. User is expected to provide a valid falling edge on WDI pin in the open window. Refer to arrive at the relevant close window and open window values needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWO time duration. An early fault is reported if a WDI falling edge is detected in close window. A late fault is reported if WDI falling edge is not detected in both close and open window. The device asserts RESET output for pinout options A, B and C or WDO output for pinout D for time tD in event of watchdog fault. Refer to arrive at the relevant tD value needed for application. shows the basic operation for window watchdog timer operation. The TPS36-Q1 watchdog functionality supports multiple features. Details are available in following sub sections. Window Watchdog Timer Operation The TPS36-Q1 offers high precision window watchdog timer monitoring. The device is available in multiple pinout options A to D which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs. The window watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled. TPS36-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer section for additional details. The window watchdog timer frame consists of two windows namely close window (tWC) followed by open window (tWO). The device monitors the WDI pin for falling edge. User is expected to provide a valid falling edge on WDI pin in the open window. Refer to arrive at the relevant close window and open window values needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWO time duration. An early fault is reported if a WDI falling edge is detected in close window. A late fault is reported if WDI falling edge is not detected in both close and open window. The device asserts RESET output for pinout options A, B and C or WDO output for pinout D for time tD in event of watchdog fault. Refer to arrive at the relevant tD value needed for application. shows the basic operation for window watchdog timer operation. The TPS36-Q1 watchdog functionality supports multiple features. Details are available in following sub sections. Window Watchdog Timer Operation The TPS36-Q1 offers high precision window watchdog timer monitoring. The device is available in multiple pinout options A to D which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs.TPS36-Q1D The window watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled. TPS36-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer section for additional details.The window watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled.IT-HYSDIT-TPS36-Q1 The window watchdog timer frame consists of two windows namely close window (tWC) followed by open window (tWO). The device monitors the WDI pin for falling edge. User is expected to provide a valid falling edge on WDI pin in the open window. Refer to arrive at the relevant close window and open window values needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWO time duration. An early fault is reported if a WDI falling edge is detected in close window. A late fault is reported if WDI falling edge is not detected in both close and open window. The device asserts RESET output for pinout options A, B and C or WDO output for pinout D for time tD in event of watchdog fault. Refer to arrive at the relevant tD value needed for application.WCWO WOThe device asserts RESET output for pinout options A, B and C or WDO output for pinout DtD D tD D shows the basic operation for window watchdog timer operation. The TPS36-Q1 watchdog functionality supports multiple features. Details are available in following sub sections.TPS36-Q1 Window Watchdog Timer Operation Window Watchdog Timer Operation tWC (Close Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The tWC timer for TPS36-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS36-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec. The TPS36-Q1 when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS36-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB to #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVB highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. tWC Equation 1 SET Pin (Pin Configuration A) SET pin value Equation 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN = 1 (Pin Configuration C, D) SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 tWC (sec) = 79.2 x 106 x CCWD (F) 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B) SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) The TPS36-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS36-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer to identify mapping of orderable part number to tWC value. tWC (Close Window) TimerWC The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The tWC timer for TPS36-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS36-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec. The TPS36-Q1 when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS36-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB to #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVB highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. tWC Equation 1 SET Pin (Pin Configuration A) SET pin value Equation 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN = 1 (Pin Configuration C, D) SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 tWC (sec) = 79.2 x 106 x CCWD (F) 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B) SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) The TPS36-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS36-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer to identify mapping of orderable part number to tWC value. The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The tWC timer for TPS36-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS36-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec. The TPS36-Q1 when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS36-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB to #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVB highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. tWC Equation 1 SET Pin (Pin Configuration A) SET pin value Equation 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN = 1 (Pin Configuration C, D) SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 tWC (sec) = 79.2 x 106 x CCWD (F) 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B) SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) The TPS36-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS36-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer to identify mapping of orderable part number to tWC value. The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The tWC timer for TPS36-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS36-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec.WCWOWCWCRESET output is asserted if pinout does not offer independent WDO output.WCTPS36-Q1s or DTPS36-Q1The TPS36-Q1 when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS36-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD capacitance. #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB to #GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVB highlights the relationship between tWC in second and CWD capacitance in farad. The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.TPS36-Q1 or after a RESET eventWCTPS36-Q1CWDCRST#GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_EPC_QP1_DVB#GUID-D3B3A4B6-F3FF-43A2-9270-9617951C20C1/TABLE_MHQ_NQ1_DVBWCWCWC tWC Equation 1 SET Pin (Pin Configuration A) SET pin value Equation 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) tWC Equation 1 SET Pin (Pin Configuration A)WC SET pin value Equation 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) SET pin value Equation SET pin value Equation SET pin valueEquation 0 tWC (sec) = 79.2 x 106 x CCWD (F) 1 tWC (sec) = 39.6 x 106 x CCWD (F) 0 tWC (sec) = 79.2 x 106 x CCWD (F) 0tWC (sec) = 79.2 x 106 x CCWD (F)WC6CWD 1 tWC (sec) = 39.6 x 106 x CCWD (F) 1tWC (sec) = 39.6 x 106 x CCWD (F)WC6CWD tWC Equation 2 SET Pin, WD-EN = 1 (Pin Configuration C, D) SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 tWC (sec) = 79.2 x 106 x CCWD (F) 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN = 1 (Pin Configuration C, D)WC SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 tWC (sec) = 79.2 x 106 x CCWD (F) 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) SET Pin Value Equation SET Pin Value Equation SET Pin ValueEquation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 tWC (sec) = 79.2 x 106 x CCWD (F) 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) 00 tWC (sec) = 79.2 x 106 x CCWD (F) 00tWC (sec) = 79.2 x 106 x CCWD (F)WC6CWD 01 tWC (sec) = 79.2 x 106 x CCWD (F) 01tWC (sec) = 79.2 x 106 x CCWD (F)WC6CWD 10 tWC (sec) = 39.6 x 106 x CCWD (F) 10tWC (sec) = 39.6 x 106 x CCWD (F)WC6CWD 11 tWC (sec) = 9.9 x 106 x CCWD (F) 11tWC (sec) = 9.9 x 106 x CCWD (F)WC6CWD tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B) SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B)WC SET Pin Value Equation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) SET Pin Value Equation SET Pin Value Equation SET Pin ValueEquation 00 tWC (sec) = 79.2 x 106 x CCWD (F) 01 Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 11 tWC (sec) = 9.9 x 106 x CCWD (F) 00 tWC (sec) = 79.2 x 106 x CCWD (F) 00tWC (sec) = 79.2 x 106 x CCWD (F)WC6CWD 01 Watchdog disabled 01Watchdog disabled 10 tWC (sec) = 39.6 x 106 x CCWD (F) 10tWC (sec) = 39.6 x 106 x CCWD (F)WC6CWD 11 tWC (sec) = 9.9 x 106 x CCWD (F) 11tWC (sec) = 9.9 x 106 x CCWD (F)WC6CWDThe TPS36-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100 sec including various industry standard values. The TPS36-Q1 fixed time options are ±10% accurate for tWC ≥ 10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the orderable part number. Refer to identify mapping of orderable part number to tWC value.TPS36-Q1WCTPS36-Q1WCWCWC WC tWO (Open Window) Timer The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition. Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault condition is detected the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the relationship between tWO and tWC. Refer to select available ratio options. tWO = (n - 1) x tWC Each orderable can offer up to 3 ratio options based on the available SET pins. Refer to identify mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC and ratio combination does not lead to tWO value greater than 640 second. tWO (Open Window) TimerWO The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition. Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault condition is detected the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the relationship between tWO and tWC. Refer to select available ratio options. tWO = (n - 1) x tWC Each orderable can offer up to 3 ratio options based on the available SET pins. Refer to identify mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC and ratio combination does not lead to tWO value greater than 640 second. The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition. Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault condition is detected the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the relationship between tWO and tWC. Refer to select available ratio options. tWO = (n - 1) x tWC Each orderable can offer up to 3 ratio options based on the available SET pins. Refer to identify mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC and ratio combination does not lead to tWO value greater than 640 second. The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition. Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault condition is detected the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. WCWOWOWOWCWORESET output is asserted if pinout does not offer independent WDO output.The tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the relationship between tWO and tWC. Refer to select available ratio options.WOWCnEquationWOWCtWO = (n - 1) x tWC WOnWCEach orderable can offer up to 3 ratio options based on the available SET pins. Refer to identify mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC and ratio combination does not lead to tWO value greater than 640 second.WOWCWO Watchdog Enable Disable Operation The TPS36-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below. Disable watchdog during firmware update to avoid host RESET. Disable watchdog during software step-by-step debug operation. Disable watchdog when performing critical task to avoid watchdog error interrupt. Keep watchdog disabled until host boots up. The TPS36-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration C,D) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two methods is available for the user to disable watchdog operation. For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The diagram shows timing behavior with WD-EN pin control. Watchdog Enable: WD-EN Pin Control SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during watchdog operation. Refer section for additional details regarding SET[1:0] pin behavior. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle or device recovery after UV fault, MR low event is needed to detect change in capacitance. Ongoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled. For a pinout with only RESET output, the RESET can assert if supply supervisor error occurs. When enabled the device immediately enters tWC frame and start watchdog monitoring operation. Watchdog Enable Disable Operation The TPS36-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below. Disable watchdog during firmware update to avoid host RESET. Disable watchdog during software step-by-step debug operation. Disable watchdog when performing critical task to avoid watchdog error interrupt. Keep watchdog disabled until host boots up. The TPS36-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration C,D) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two methods is available for the user to disable watchdog operation. For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The diagram shows timing behavior with WD-EN pin control. Watchdog Enable: WD-EN Pin Control SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during watchdog operation. Refer section for additional details regarding SET[1:0] pin behavior. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle or device recovery after UV fault, MR low event is needed to detect change in capacitance. Ongoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled. For a pinout with only RESET output, the RESET can assert if supply supervisor error occurs. When enabled the device immediately enters tWC frame and start watchdog monitoring operation. The TPS36-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below. Disable watchdog during firmware update to avoid host RESET. Disable watchdog during software step-by-step debug operation. Disable watchdog when performing critical task to avoid watchdog error interrupt. Keep watchdog disabled until host boots up. The TPS36-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration C,D) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two methods is available for the user to disable watchdog operation. For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The diagram shows timing behavior with WD-EN pin control. Watchdog Enable: WD-EN Pin Control SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during watchdog operation. Refer section for additional details regarding SET[1:0] pin behavior. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle or device recovery after UV fault, MR low event is needed to detect change in capacitance. Ongoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled. For a pinout with only RESET output, the RESET can assert if supply supervisor error occurs. When enabled the device immediately enters tWC frame and start watchdog monitoring operation. The TPS36-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use cases as listed below.TPS36-Q1 Disable watchdog during firmware update to avoid host RESET. Disable watchdog during software step-by-step debug operation. Disable watchdog when performing critical task to avoid watchdog error interrupt. Keep watchdog disabled until host boots up. Disable watchdog during firmware update to avoid host RESET.Disable watchdog during software step-by-step debug operation.Disable watchdog when performing critical task to avoid watchdog error interrupt.Keep watchdog disabled until host boots up.The TPS36-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration C,D) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two methods is available for the user to disable watchdog operation.TPS36-Q1For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog operation. The WD-EN pin can be toggled any time during the device operation. The diagram shows timing behavior with WD-EN pin control. Watchdog Enable: WD-EN Pin Control Watchdog Enable: WD-EN Pin ControlSET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during watchdog operation. Refer section for additional details regarding SET[1:0] pin behavior. Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing capacitance on the fly does not enable or disable watchdog operation. A power supply recycle or device recovery after UV fault, MR low event is needed to detect change in capacitance. or device recovery after UV fault, MR low eventMROngoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled. For a pinout with only RESET output, the RESET can assert if supply supervisor error occurs. When enabled the device immediately enters tWC frame and start watchdog monitoring operation.For a pinout with only RESET output, the RESET can assert if supply supervisor error occurs. tWC WC tSD Watchdog Start Up Delay The TPS36-Q1 supports watchdog startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO or RESET assert events during boot. The tSD time is predetermined based on the device part number selected. Refer section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options. The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin. For devices with only RESET output, the RESET pin is asserted. The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin or WDI float functionality as described in section. shows the operation for tSD time frame. tSD Frame Behavior tSD Watchdog Start Up DelaySD The TPS36-Q1 supports watchdog startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO or RESET assert events during boot. The tSD time is predetermined based on the device part number selected. Refer section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options. The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin. For devices with only RESET output, the RESET pin is asserted. The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin or WDI float functionality as described in section. shows the operation for tSD time frame. tSD Frame Behavior The TPS36-Q1 supports watchdog startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO or RESET assert events during boot. The tSD time is predetermined based on the device part number selected. Refer section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options. The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin. For devices with only RESET output, the RESET pin is asserted. The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin or WDI float functionality as described in section. shows the operation for tSD time frame. tSD Frame Behavior The TPS36-Q1 supports watchdog startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO or RESET assert events during boot. The tSD time is predetermined based on the device part number selected. Refer section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options.TPS36-Q1or after a RESET assert event SD or RESETSD SDThe tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI pin triggers the watchdog error by asserting the WDO output pin. For devices with only RESET output, the RESET pin is asserted. SDSDSDSD For devices with only RESET output, the RESET pin is asserted.The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin or WDI float functionality as described in section.SD shows the operation for tSD time frame.SD tSD Frame Behavior tSD Frame BehaviorSD SET Pin Behavior The TPS36-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep. Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated. For a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec. tWO Values with SET0 Pin Only (Pin Configuration A) Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec Pinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin. tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B) Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec Example for Watchdog Close Time setting = 100 msec. Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec. to show the timing behavior with respect to SETx status changes. Watchdog Behavior with SETx Pin Status Watchdog Operation with 2 SET Pins Watchdog Operation with 1 SET Pin SET Pin Behavior The TPS36-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep. Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated. For a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec. tWO Values with SET0 Pin Only (Pin Configuration A) Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec Pinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin. tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B) Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec Example for Watchdog Close Time setting = 100 msec. Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec. to show the timing behavior with respect to SETx status changes. Watchdog Behavior with SETx Pin Status Watchdog Operation with 2 SET Pins Watchdog Operation with 1 SET Pin The TPS36-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep. Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated. For a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec. tWO Values with SET0 Pin Only (Pin Configuration A) Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec Pinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin. tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B) Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec Example for Watchdog Close Time setting = 100 msec. Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec. to show the timing behavior with respect to SETx status changes. Watchdog Behavior with SETx Pin Status Watchdog Operation with 2 SET Pins Watchdog Operation with 1 SET Pin The TPS36-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET pin can be used areTPS36-Q1WO Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep. Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete. Use wide open window timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep.Change to wide open window timer when performing system critical tasks to ensure watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete.The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector in the section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWO timer value will be applied after output is deasserted and the tSD timer is over or terminated.WOWCWC or RESETWOSDFor a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. showcases an example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D = 10 msec.WO WO tWO Values with SET0 Pin Only (Pin Configuration A) Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec tWO Values with SET0 Pin Only (Pin Configuration A)WO Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec Watchdog Open Time Ratio Selection tWO SET0 = 0 SET0 = 1 Watchdog Open Time Ratio Selection tWO Watchdog Open Time Ratio Selection Watchdog Open Time Ratio Selection tWO tWO WO SET0 = 0 SET0 = 1 SET0 = 0 SET0 = 0 SET0 = 1 SET0 = 1 A 10 msec 30 msec B 30 msec 70 msec C 70 msec 150 msec D 150 msec 310 msec E 310 msec 630 msec F 630 msec 1270 msec A 10 msec 30 msec A10 msec30 msec B 30 msec 70 msec B30 msec70 msec C 70 msec 150 msec C70 msec150 msec D 150 msec 310 msec D150 msec310 msec E 310 msec 630 msec E310 msec630 msec F 630 msec 1270 msec F630 msec1270 msecPinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog Open Time Ratio selector field in the orderable part number. Refer for available options. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin.WO WO tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B) Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B)WO Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec Watchdog Open Time Ratio selection tWO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 Watchdog Open Time Ratio selection tWO Watchdog Open Time Ratio selection Watchdog Open Time Ratio selection tWO tWO WO SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'11 SET[1:0] = 0b'00 SET[1:0] = 0b'00 SET[1:0] = 0b'01 SET[1:0] = 0b'01 SET[1:0] = 0b'10 SET[1:0] = 0b'10 SET[1:0] = 0b'11 SET[1:0] = 0b'11 A 100 msec Watchdog disable 300 msec 1500 msec B 300 msec Watchdog disable 700 msec 3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec A 100 msec Watchdog disable 300 msec 1500 msec A100 msecWatchdog disable300 msec1500 msec B 300 msec Watchdog disable 700 msec 3100 msec B300 msecWatchdog disable700 msec3100 msec C 700 msec Watchdog disable 1500 msec 6300 msec C700 msecWatchdog disable1500 msec6300 msec D 1500 msec Watchdog disable 3100 msec 12700 msec D1500 msecWatchdog disable3100 msec12700 msec E 3100 msec Watchdog disable 6300 msec 25500 msec E3100 msecWatchdog disable6300 msec25500 msec F 6300 msec Watchdog disable 12700 msec 51100 msec F6300 msecWatchdog disable12700 msec51100 msec Example for Watchdog Close Time setting = 100 msec. Example for Watchdog Close Time setting = 100 msec.Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00. Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio results in tWO > 640 sec, the timer value will be restricted to 640 sec.WOWO to show the timing behavior with respect to SETx status changes. Watchdog Behavior with SETx Pin Status Watchdog Behavior with SETx Pin Status Watchdog Operation with 2 SET Pins Watchdog Operation with 2 SET Pins Watchdog Operation with 1 SET Pin Watchdog Operation with 1 SET Pin Manual RESET The TPS36-Q1 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than 0.3 x VDD, asserts the RESET output. The MR pin has 100 kΩ pull up to VDD. The MR pin can be left floating. The internal pull up will ensure the output is not asserted due to MR pin trigger. The output is deasserted after MR pin voltage rises above 0.7 x VDD voltage and time tD is elapsed. Refer for more details. MR Pin Response Manual RESET The TPS36-Q1 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than 0.3 x VDD, asserts the RESET output. The MR pin has 100 kΩ pull up to VDD. The MR pin can be left floating. The internal pull up will ensure the output is not asserted due to MR pin trigger. The output is deasserted after MR pin voltage rises above 0.7 x VDD voltage and time tD is elapsed. Refer for more details. MR Pin Response The TPS36-Q1 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than 0.3 x VDD, asserts the RESET output. The MR pin has 100 kΩ pull up to VDD. The MR pin can be left floating. The internal pull up will ensure the output is not asserted due to MR pin trigger. The output is deasserted after MR pin voltage rises above 0.7 x VDD voltage and time tD is elapsed. Refer for more details. MR Pin Response The TPS36-Q1 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than 0.3 x VDD, asserts the RESET output. The MR pin has 100 kΩ pull up to VDD. The MR pin can be left floating. The internal pull up will ensure the output is not asserted due to MR pin trigger.TPS36-Q1MRMRRESETMRMRMRThe output is deasserted after MR pin voltage rises above 0.7 x VDD voltage and time tD is elapsed. Refer for more details.MR and time tD is elapsedD MR Pin Response MR Pin ResponseMR RESET and WDO Output The TPS36-Q1 device can offer RESET or RESET with independent WDO output pin. The output configuration is dependent on the pinout variant selected. For a pinout which has only RESET output, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold or watchdog timer error is detected. For a pinout which has independent RESET and WDO output pins, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold. WDO output is asserted only when watchdog timer error is detected. RESET error has higher priority than WDO error. If RESET is asserted when WDO is asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin is deasserted and startup delay frame is terminated. The output will be asserted for tD time when any relevant events described above are detected. The time tD can be programmed by connecting a capacitor between CRST pin and GND or device will assert tD for fixed time duration as selected by orderable part number. Refer section for all available options. describes the relationship between capacitor value and the time tD . Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. t D (sec) = 4.95 x 106 x CCRST (F) TPS36-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to voltage supervisor undervoltage detection, the output latch will be released when VDD voltage rises above the VIT- + VHYS level. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. shows timing behavior of the device with latched output configuration. Output Latch Timing Behavior RESET and WDO OutputRESET and The TPS36-Q1 device can offer RESET or RESET with independent WDO output pin. The output configuration is dependent on the pinout variant selected. For a pinout which has only RESET output, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold or watchdog timer error is detected. For a pinout which has independent RESET and WDO output pins, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold. WDO output is asserted only when watchdog timer error is detected. RESET error has higher priority than WDO error. If RESET is asserted when WDO is asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin is deasserted and startup delay frame is terminated. The output will be asserted for tD time when any relevant events described above are detected. The time tD can be programmed by connecting a capacitor between CRST pin and GND or device will assert tD for fixed time duration as selected by orderable part number. Refer section for all available options. describes the relationship between capacitor value and the time tD . Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. t D (sec) = 4.95 x 106 x CCRST (F) TPS36-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to voltage supervisor undervoltage detection, the output latch will be released when VDD voltage rises above the VIT- + VHYS level. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. shows timing behavior of the device with latched output configuration. Output Latch Timing Behavior The TPS36-Q1 device can offer RESET or RESET with independent WDO output pin. The output configuration is dependent on the pinout variant selected. For a pinout which has only RESET output, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold or watchdog timer error is detected. For a pinout which has independent RESET and WDO output pins, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold. WDO output is asserted only when watchdog timer error is detected. RESET error has higher priority than WDO error. If RESET is asserted when WDO is asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin is deasserted and startup delay frame is terminated. The output will be asserted for tD time when any relevant events described above are detected. The time tD can be programmed by connecting a capacitor between CRST pin and GND or device will assert tD for fixed time duration as selected by orderable part number. Refer section for all available options. describes the relationship between capacitor value and the time tD . Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device. t D (sec) = 4.95 x 106 x CCRST (F) TPS36-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to voltage supervisor undervoltage detection, the output latch will be released when VDD voltage rises above the VIT- + VHYS level. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. shows timing behavior of the device with latched output configuration. Output Latch Timing Behavior The TPS36-Q1 device can offer RESET or RESET with independent WDO output pin. The output configuration is dependent on the pinout variant selected. For a pinout which has only RESET output, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold or watchdog timer error is detected. For a pinout which has independent RESET and WDO output pins, the RESET output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold. WDO output is asserted only when watchdog timer error is detected. RESET error has higher priority than WDO error. If RESET is asserted when WDO is asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin is deasserted and startup delay frame is terminated.TPS36-Q1MRMRThe output will be asserted for tD time when any relevant events described above are detected. The time tD can be programmed by connecting a capacitor between CRST pin and GND or device will assert tD for fixed time duration as selected by orderable part number. Refer section for all available options.tD DtD DtD D describes the relationship between capacitor value and the time tD . Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.tD D t D (sec) = 4.95 x 106 x CCRST (F) t D (sec) = 4.95 x 106 x CCRST (F) D D6CRST TPS36-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is latched due to voltage supervisor undervoltage detection, the output latch will be released when VDD voltage rises above the VIT- + VHYS level. If the output is latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered up again. shows timing behavior of the device with latched output configuration.TPS36-Q1If the output is latched due to voltage supervisor undervoltage detection, the output latch will be released when VDD voltage rises above the VIT- + VHYS level. IT-HYSMRMRDD Output Latch Timing Behavior Output Latch Timing Behavior Device Functional Modes #GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/A_1467996961_SHEET1 summarizes the functional modes of the TPS36-Q1. Device Functional Modes VDD WATCHDOG STATUS WDI WDO RESET VDD < VPOR Not Applicable — Undefined Undefined VPOR ≤ VDD < VIT- Not Applicable Ignored High Low VDD ≥ VIT+ Disabled Ignored High High Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High High Enabled tWC(max) > tpulse 1 Low High Enabled tWC(max) + tWO(max) < tpulse 1 Low High Where tpulse is the time between falling edges on WDI. Device Functional Modes #GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/A_1467996961_SHEET1 summarizes the functional modes of the TPS36-Q1. Device Functional Modes VDD WATCHDOG STATUS WDI WDO RESET VDD < VPOR Not Applicable — Undefined Undefined VPOR ≤ VDD < VIT- Not Applicable Ignored High Low VDD ≥ VIT+ Disabled Ignored High High Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High High Enabled tWC(max) > tpulse 1 Low High Enabled tWC(max) + tWO(max) < tpulse 1 Low High Where tpulse is the time between falling edges on WDI. #GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/A_1467996961_SHEET1 summarizes the functional modes of the TPS36-Q1. Device Functional Modes VDD WATCHDOG STATUS WDI WDO RESET VDD < VPOR Not Applicable — Undefined Undefined VPOR ≤ VDD < VIT- Not Applicable Ignored High Low VDD ≥ VIT+ Disabled Ignored High High Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High High Enabled tWC(max) > tpulse 1 Low High Enabled tWC(max) + tWO(max) < tpulse 1 Low High Where tpulse is the time between falling edges on WDI. #GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/A_1467996961_SHEET1 summarizes the functional modes of the TPS36-Q1. #GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/A_1467996961_SHEET1 #GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/A_1467996961_SHEET1TPS36-Q1 Device Functional Modes VDD WATCHDOG STATUS WDI WDO RESET VDD < VPOR Not Applicable — Undefined Undefined VPOR ≤ VDD < VIT- Not Applicable Ignored High Low VDD ≥ VIT+ Disabled Ignored High High Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High High Enabled tWC(max) > tpulse 1 Low High Enabled tWC(max) + tWO(max) < tpulse 1 Low High Device Functional Modes VDD WATCHDOG STATUS WDI WDO RESET VDD < VPOR Not Applicable — Undefined Undefined VPOR ≤ VDD < VIT- Not Applicable Ignored High Low VDD ≥ VIT+ Disabled Ignored High High Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High High Enabled tWC(max) > tpulse 1 Low High Enabled tWC(max) + tWO(max) < tpulse 1 Low High VDD WATCHDOG STATUS WDI WDO RESET VDD WATCHDOG STATUS WDI WDO RESET VDDWATCHDOG STATUSWDI WDO WDO RESET RESET VDD < VPOR Not Applicable — Undefined Undefined VPOR ≤ VDD < VIT- Not Applicable Ignored High Low VDD ≥ VIT+ Disabled Ignored High High Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High High Enabled tWC(max) > tpulse 1 Low High Enabled tWC(max) + tWO(max) < tpulse 1 Low High VDD < VPOR Not Applicable — Undefined Undefined VDD < VPOR DDPORNot Applicable—UndefinedUndefined VPOR ≤ VDD < VIT- Not Applicable Ignored High Low VPOR ≤ VDD < VIT- PORDDIT-Not ApplicableIgnoredHighLow VDD ≥ VIT+ Disabled Ignored High High VDD ≥ VIT+ DDIT+DisabledIgnoredHighHigh Enabled tWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) High High EnabledtWC(max) ≤ tpulse 1 ≤ tWC(max) + tWO(min) WC(max)pulse1WC(max)WO(min)HighHigh Enabled tWC(max) > tpulse 1 Low High EnabledtWC(max) > tpulse 1 WC(max)pulse1LowHigh Enabled tWC(max) + tWO(max) < tpulse 1 Low High EnabledtWC(max) + tWO(max) < tpulse 1 WC(max)WO(max)pulse1LowHigh Where tpulse is the time between falling edges on WDI. Where tpulse is the time between falling edges on WDI.pulse Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Application Information The following sections describe in detail proper device implementation, depending on the final application requirements. CRST Delay The TPS36-Q1 features two options for setting the reset delay (tD): using a fixed timing and programming the timing through an external capacitor. Factory-Programmed Reset Delay Timing Fixed reset delay timings are available using pinouts C and D. Using these timings enables a high-precision, 10% accurate reset delay timing. Adjustable Capacitor Timing The TPS36-Q1 also offers programmable reset delay option when using pinout A and B. The TPS36-Q1 can be programmed to have a desired reset delay by connecting a capacitor between CRST pin and GND. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12 , where tD is the reset delay time in seconds and CCRST is the capacitance in farads. tD (sec) = 4.95 × 106 × CCRST (F) To minimize the difference between the calculated reset delay time and the actual reset delay time, use a use a high-quality ceramic dielectric COG capacitor and minimize parasitic board capacitance around this pin. #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026 lists the reset delay time ideal capacitor values for CCRST. Reset Delay Time for Common Ideal Capacitor Values CCRST RESETDELAY TIME (tD) UNIT MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 TYP MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms Minimum and maximum values are calculated using ideal capacitors. Watchdog Window Functionality The TPS36-Q1 features two options for setting the close window watchdog timer (tWC ): using a fixed timing and programming the timing through an external capacitor. Factory-Programmed watchdog Timing Fixed watchdog window close timings are available using pinout C and D. Using these timings enables a high-precision, 10% accurate watchdog timer tWC. Adjustable Capacitor Timing Pinout options A and B support adjustable tWC timing. This is achievable by connecting a capacitor between CWD and GND pin. Consult , , and for calculating typical tWC values using ideal capacitors. Capacitor tolerances will cause additional deviation. For the most accurate timing, use ceramic capacitors with COG dielectric material. Typical Applications Design 1: Monitoring Microcontroller Supply and Watchdog During Operational and Sleep Modes The TPS36-Q1 can utilize high-accuracy voltage monitoring and on-the-fly SETx assigning to monitor a microcontroller that has both an operational and sleep mode. Monitoring Microcontroller Supply and Watchdog During Operation and Sleep Design Requirements Design Parameters PARAMETER DESIGN REQUIREMENT DESIGN RESULT Voltage Threshold Typical Voltage Threshold of 1.65 V Typical Voltage Threshold of 1.65 V Window Close Time During Operation Typical tWC of 50 ms during opertation Typical tWC of 50 ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50 ms Window Open Time During Sleep Typical tWO of 12 s during operation Typical tWO of 12.75 s RESET Delay 200 ms 200 ms Output Logic Open-drain Open-drain Maximum Device Current Consumption 20 μA 250 nA typical, 3 μA maximum Detailed Design Procedure Setting Voltage Threshold The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number. OPN "Threshold Voltage" number = (VIT- - 1) / 0.05 In this example, the nominal supply voltage for the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the device is reset just before the supply voltage reaches the minimum allowed. Thus a 1.65 V threshold is chosen and, using #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB, the part number is reduced to TPS36xx13xxxxxxxQ1. The hysteresis is 5% typical, resulting in a positive-going threshold voltage, VIT+, of 1.73 V. Determining Window Timings During Operation and Sleep Modes The TPS36-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a minimum watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS36xx13FExDDFRQ1. Meeting the Minimum Reset Delay The TPS36-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS36-Q1 supports only fixed watchdog timings and fixed reset delays or programmable watchdog timings and programmable reset delays. The application requires a 200 ms minimum reset delay, thus reset delay option G is used. Because of these requirements and no need for a startup delay, the TPS36CA13FEGDDFRQ1 is used. Setting the Watchdog Window In this application, the watchdog timing options are based on the WDI signal that is provided to the TPS36-Q1. A watchdog WDI setting must be chosen such that a transition must always occur within the open watchdog window. There are several ways to achieve these window parameters. An external capacitor can be placed on the CWD pin and calculated to have a sufficient window close time. Another option is to use one of the factory-programmed timing options. An additional advantage of choosing one of the factory-programmed options is the ability to reduce the number of components required, thus reducing overall BOM cost. Calculating the RESET Pullup Resistor The TPS36-Q1 uses an open-drain configuration for the RESET output, as shown in .When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted. Open-Drain RESET Configuration Power Supply Recommendations This device is designed to operate from an input supply with a voltage range between 1.04 V and 6 V. An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. Layout Layout Guidelines Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected. Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin. Place CCRST capacitor as close as possible to the CRST pin. Place CCWD capacitor as close as possible to the CWD pin. Place the pullup resistor on the RESET pin as close to the pin as possible. Layout Example Typical Layout for the pinout C of TPS36-Q1 Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Application Information The following sections describe in detail proper device implementation, depending on the final application requirements. CRST Delay The TPS36-Q1 features two options for setting the reset delay (tD): using a fixed timing and programming the timing through an external capacitor. Factory-Programmed Reset Delay Timing Fixed reset delay timings are available using pinouts C and D. Using these timings enables a high-precision, 10% accurate reset delay timing. Adjustable Capacitor Timing The TPS36-Q1 also offers programmable reset delay option when using pinout A and B. The TPS36-Q1 can be programmed to have a desired reset delay by connecting a capacitor between CRST pin and GND. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12 , where tD is the reset delay time in seconds and CCRST is the capacitance in farads. tD (sec) = 4.95 × 106 × CCRST (F) To minimize the difference between the calculated reset delay time and the actual reset delay time, use a use a high-quality ceramic dielectric COG capacitor and minimize parasitic board capacitance around this pin. #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026 lists the reset delay time ideal capacitor values for CCRST. Reset Delay Time for Common Ideal Capacitor Values CCRST RESETDELAY TIME (tD) UNIT MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 TYP MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms Minimum and maximum values are calculated using ideal capacitors. Watchdog Window Functionality The TPS36-Q1 features two options for setting the close window watchdog timer (tWC ): using a fixed timing and programming the timing through an external capacitor. Factory-Programmed watchdog Timing Fixed watchdog window close timings are available using pinout C and D. Using these timings enables a high-precision, 10% accurate watchdog timer tWC. Adjustable Capacitor Timing Pinout options A and B support adjustable tWC timing. This is achievable by connecting a capacitor between CWD and GND pin. Consult , , and for calculating typical tWC values using ideal capacitors. Capacitor tolerances will cause additional deviation. For the most accurate timing, use ceramic capacitors with COG dielectric material. Application Information The following sections describe in detail proper device implementation, depending on the final application requirements. The following sections describe in detail proper device implementation, depending on the final application requirements. The following sections describe in detail proper device implementation, depending on the final application requirements. CRST Delay The TPS36-Q1 features two options for setting the reset delay (tD): using a fixed timing and programming the timing through an external capacitor. Factory-Programmed Reset Delay Timing Fixed reset delay timings are available using pinouts C and D. Using these timings enables a high-precision, 10% accurate reset delay timing. Adjustable Capacitor Timing The TPS36-Q1 also offers programmable reset delay option when using pinout A and B. The TPS36-Q1 can be programmed to have a desired reset delay by connecting a capacitor between CRST pin and GND. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12 , where tD is the reset delay time in seconds and CCRST is the capacitance in farads. tD (sec) = 4.95 × 106 × CCRST (F) To minimize the difference between the calculated reset delay time and the actual reset delay time, use a use a high-quality ceramic dielectric COG capacitor and minimize parasitic board capacitance around this pin. #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026 lists the reset delay time ideal capacitor values for CCRST. Reset Delay Time for Common Ideal Capacitor Values CCRST RESETDELAY TIME (tD) UNIT MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 TYP MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms Minimum and maximum values are calculated using ideal capacitors. CRST Delay The TPS36-Q1 features two options for setting the reset delay (tD): using a fixed timing and programming the timing through an external capacitor. The TPS36-Q1 features two options for setting the reset delay (tD): using a fixed timing and programming the timing through an external capacitor. The TPS36-Q1 features two options for setting the reset delay (tD): using a fixed timing and programming the timing through an external capacitor.TPS36-Q1 (tD)D Factory-Programmed Reset Delay Timing Fixed reset delay timings are available using pinouts C and D. Using these timings enables a high-precision, 10% accurate reset delay timing. Factory-Programmed Reset Delay Timing Fixed reset delay timings are available using pinouts C and D. Using these timings enables a high-precision, 10% accurate reset delay timing. Fixed reset delay timings are available using pinouts C and D. Using these timings enables a high-precision, 10% accurate reset delay timing. Fixed reset delay timings are available using pinouts C and D. Using these timings enables a high-precision, 10% accurate reset delay timing. Adjustable Capacitor Timing The TPS36-Q1 also offers programmable reset delay option when using pinout A and B. The TPS36-Q1 can be programmed to have a desired reset delay by connecting a capacitor between CRST pin and GND. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12 , where tD is the reset delay time in seconds and CCRST is the capacitance in farads. tD (sec) = 4.95 × 106 × CCRST (F) To minimize the difference between the calculated reset delay time and the actual reset delay time, use a use a high-quality ceramic dielectric COG capacitor and minimize parasitic board capacitance around this pin. #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026 lists the reset delay time ideal capacitor values for CCRST. Reset Delay Time for Common Ideal Capacitor Values CCRST RESETDELAY TIME (tD) UNIT MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 TYP MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms Minimum and maximum values are calculated using ideal capacitors. Adjustable Capacitor Timing The TPS36-Q1 also offers programmable reset delay option when using pinout A and B. The TPS36-Q1 can be programmed to have a desired reset delay by connecting a capacitor between CRST pin and GND. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12 , where tD is the reset delay time in seconds and CCRST is the capacitance in farads. tD (sec) = 4.95 × 106 × CCRST (F) To minimize the difference between the calculated reset delay time and the actual reset delay time, use a use a high-quality ceramic dielectric COG capacitor and minimize parasitic board capacitance around this pin. #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026 lists the reset delay time ideal capacitor values for CCRST. Reset Delay Time for Common Ideal Capacitor Values CCRST RESETDELAY TIME (tD) UNIT MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 TYP MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms Minimum and maximum values are calculated using ideal capacitors. The TPS36-Q1 also offers programmable reset delay option when using pinout A and B. The TPS36-Q1 can be programmed to have a desired reset delay by connecting a capacitor between CRST pin and GND. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12 , where tD is the reset delay time in seconds and CCRST is the capacitance in farads. tD (sec) = 4.95 × 106 × CCRST (F) To minimize the difference between the calculated reset delay time and the actual reset delay time, use a use a high-quality ceramic dielectric COG capacitor and minimize parasitic board capacitance around this pin. #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026 lists the reset delay time ideal capacitor values for CCRST. Reset Delay Time for Common Ideal Capacitor Values CCRST RESETDELAY TIME (tD) UNIT MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 TYP MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms Minimum and maximum values are calculated using ideal capacitors. The TPS36-Q1 also offers programmable reset delay option when using pinout A and B. The TPS36-Q1 can be programmed to have a desired reset delay by connecting a capacitor between CRST pin and GND. The typical delay time resulting from a given external capacitance on the CRST pin can be calculated by #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12 , where tD is the reset delay time in seconds and CCRST is the capacitance in farads.TPS36-Q1TPS36-Q1#GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12DCRSTtD (sec) = 4.95 × 106 × CCRST (F)D6CRSTTo minimize the difference between the calculated reset delay time and the actual reset delay time, use a use a high-quality ceramic dielectric COG capacitor and minimize parasitic board capacitance around this pin. #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026 lists the reset delay time ideal capacitor values for CCRST.#GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026CRST Reset Delay Time for Common Ideal Capacitor Values CCRST RESETDELAY TIME (tD) UNIT MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 TYP MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms Reset Delay Time for Common Ideal Capacitor Values CCRST RESETDELAY TIME (tD) UNIT MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 TYP MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms CCRST RESETDELAY TIME (tD) UNIT MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 TYP MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 CCRST RESETDELAY TIME (tD) UNIT CCRST CRST RESETDELAY TIME (tD)RESETDUNIT MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 TYP MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39TYPMAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39 10 nF 39.6 49.5 59.4 ms 100 nF 396 495 594 ms 1 μF 3960 4950 5940 ms 10 nF 39.6 49.5 59.4 ms 10 nF39.649.559.4ms 100 nF 396 495 594 ms 100 nF396495594ms 1 μF 3960 4950 5940 ms 1 μF396049505940ms Minimum and maximum values are calculated using ideal capacitors. Minimum and maximum values are calculated using ideal capacitors. Watchdog Window Functionality The TPS36-Q1 features two options for setting the close window watchdog timer (tWC ): using a fixed timing and programming the timing through an external capacitor. Factory-Programmed watchdog Timing Fixed watchdog window close timings are available using pinout C and D. Using these timings enables a high-precision, 10% accurate watchdog timer tWC. Adjustable Capacitor Timing Pinout options A and B support adjustable tWC timing. This is achievable by connecting a capacitor between CWD and GND pin. Consult , , and for calculating typical tWC values using ideal capacitors. Capacitor tolerances will cause additional deviation. For the most accurate timing, use ceramic capacitors with COG dielectric material. Watchdog Window FunctionalityWindow The TPS36-Q1 features two options for setting the close window watchdog timer (tWC ): using a fixed timing and programming the timing through an external capacitor. The TPS36-Q1 features two options for setting the close window watchdog timer (tWC ): using a fixed timing and programming the timing through an external capacitor. The TPS36-Q1 features two options for setting the close window watchdog timer (tWC ): using a fixed timing and programming the timing through an external capacitor.TPS36-Q1close window tWC WC Factory-Programmed watchdog Timing Fixed watchdog window close timings are available using pinout C and D. Using these timings enables a high-precision, 10% accurate watchdog timer tWC. Factory-Programmed watchdog Timing Fixed watchdog window close timings are available using pinout C and D. Using these timings enables a high-precision, 10% accurate watchdog timer tWC. Fixed watchdog window close timings are available using pinout C and D. Using these timings enables a high-precision, 10% accurate watchdog timer tWC. Fixed watchdog window close timings are available using pinout C and D. Using these timings enables a high-precision, 10% accurate watchdog timer tWC.WC Adjustable Capacitor Timing Pinout options A and B support adjustable tWC timing. This is achievable by connecting a capacitor between CWD and GND pin. Consult , , and for calculating typical tWC values using ideal capacitors. Capacitor tolerances will cause additional deviation. For the most accurate timing, use ceramic capacitors with COG dielectric material. Adjustable Capacitor Timing Pinout options A and B support adjustable tWC timing. This is achievable by connecting a capacitor between CWD and GND pin. Consult , , and for calculating typical tWC values using ideal capacitors. Capacitor tolerances will cause additional deviation. For the most accurate timing, use ceramic capacitors with COG dielectric material. Pinout options A and B support adjustable tWC timing. This is achievable by connecting a capacitor between CWD and GND pin. Consult , , and for calculating typical tWC values using ideal capacitors. Capacitor tolerances will cause additional deviation. For the most accurate timing, use ceramic capacitors with COG dielectric material. Pinout options A and B support adjustable tWC timing. This is achievable by connecting a capacitor between CWD and GND pin. Consult , , and for calculating typical tWC values using ideal capacitors. Capacitor tolerances will cause additional deviation. For the most accurate timing, use ceramic capacitors with COG dielectric material.WCWC Typical Applications Design 1: Monitoring Microcontroller Supply and Watchdog During Operational and Sleep Modes The TPS36-Q1 can utilize high-accuracy voltage monitoring and on-the-fly SETx assigning to monitor a microcontroller that has both an operational and sleep mode. Monitoring Microcontroller Supply and Watchdog During Operation and Sleep Design Requirements Design Parameters PARAMETER DESIGN REQUIREMENT DESIGN RESULT Voltage Threshold Typical Voltage Threshold of 1.65 V Typical Voltage Threshold of 1.65 V Window Close Time During Operation Typical tWC of 50 ms during opertation Typical tWC of 50 ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50 ms Window Open Time During Sleep Typical tWO of 12 s during operation Typical tWO of 12.75 s RESET Delay 200 ms 200 ms Output Logic Open-drain Open-drain Maximum Device Current Consumption 20 μA 250 nA typical, 3 μA maximum Detailed Design Procedure Setting Voltage Threshold The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number. OPN "Threshold Voltage" number = (VIT- - 1) / 0.05 In this example, the nominal supply voltage for the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the device is reset just before the supply voltage reaches the minimum allowed. Thus a 1.65 V threshold is chosen and, using #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB, the part number is reduced to TPS36xx13xxxxxxxQ1. The hysteresis is 5% typical, resulting in a positive-going threshold voltage, VIT+, of 1.73 V. Determining Window Timings During Operation and Sleep Modes The TPS36-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a minimum watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS36xx13FExDDFRQ1. Meeting the Minimum Reset Delay The TPS36-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS36-Q1 supports only fixed watchdog timings and fixed reset delays or programmable watchdog timings and programmable reset delays. The application requires a 200 ms minimum reset delay, thus reset delay option G is used. Because of these requirements and no need for a startup delay, the TPS36CA13FEGDDFRQ1 is used. Setting the Watchdog Window In this application, the watchdog timing options are based on the WDI signal that is provided to the TPS36-Q1. A watchdog WDI setting must be chosen such that a transition must always occur within the open watchdog window. There are several ways to achieve these window parameters. An external capacitor can be placed on the CWD pin and calculated to have a sufficient window close time. Another option is to use one of the factory-programmed timing options. An additional advantage of choosing one of the factory-programmed options is the ability to reduce the number of components required, thus reducing overall BOM cost. Calculating the RESET Pullup Resistor The TPS36-Q1 uses an open-drain configuration for the RESET output, as shown in .When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted. Open-Drain RESET Configuration Typical Applications Design 1: Monitoring Microcontroller Supply and Watchdog During Operational and Sleep Modes The TPS36-Q1 can utilize high-accuracy voltage monitoring and on-the-fly SETx assigning to monitor a microcontroller that has both an operational and sleep mode. Monitoring Microcontroller Supply and Watchdog During Operation and Sleep Design Requirements Design Parameters PARAMETER DESIGN REQUIREMENT DESIGN RESULT Voltage Threshold Typical Voltage Threshold of 1.65 V Typical Voltage Threshold of 1.65 V Window Close Time During Operation Typical tWC of 50 ms during opertation Typical tWC of 50 ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50 ms Window Open Time During Sleep Typical tWO of 12 s during operation Typical tWO of 12.75 s RESET Delay 200 ms 200 ms Output Logic Open-drain Open-drain Maximum Device Current Consumption 20 μA 250 nA typical, 3 μA maximum Detailed Design Procedure Setting Voltage Threshold The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number. OPN "Threshold Voltage" number = (VIT- - 1) / 0.05 In this example, the nominal supply voltage for the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the device is reset just before the supply voltage reaches the minimum allowed. Thus a 1.65 V threshold is chosen and, using #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB, the part number is reduced to TPS36xx13xxxxxxxQ1. The hysteresis is 5% typical, resulting in a positive-going threshold voltage, VIT+, of 1.73 V. Determining Window Timings During Operation and Sleep Modes The TPS36-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a minimum watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS36xx13FExDDFRQ1. Meeting the Minimum Reset Delay The TPS36-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS36-Q1 supports only fixed watchdog timings and fixed reset delays or programmable watchdog timings and programmable reset delays. The application requires a 200 ms minimum reset delay, thus reset delay option G is used. Because of these requirements and no need for a startup delay, the TPS36CA13FEGDDFRQ1 is used. Setting the Watchdog Window In this application, the watchdog timing options are based on the WDI signal that is provided to the TPS36-Q1. A watchdog WDI setting must be chosen such that a transition must always occur within the open watchdog window. There are several ways to achieve these window parameters. An external capacitor can be placed on the CWD pin and calculated to have a sufficient window close time. Another option is to use one of the factory-programmed timing options. An additional advantage of choosing one of the factory-programmed options is the ability to reduce the number of components required, thus reducing overall BOM cost. Calculating the RESET Pullup Resistor The TPS36-Q1 uses an open-drain configuration for the RESET output, as shown in .When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted. Open-Drain RESET Configuration Design 1: Monitoring Microcontroller Supply and Watchdog During Operational and Sleep Modes The TPS36-Q1 can utilize high-accuracy voltage monitoring and on-the-fly SETx assigning to monitor a microcontroller that has both an operational and sleep mode. Monitoring Microcontroller Supply and Watchdog During Operation and Sleep The TPS36-Q1 can utilize high-accuracy voltage monitoring and on-the-fly SETx assigning to monitor a microcontroller that has both an operational and sleep mode. Monitoring Microcontroller Supply and Watchdog During Operation and Sleep The TPS36-Q1 can utilize high-accuracy voltage monitoring and on-the-fly SETx assigning to monitor a microcontroller that has both an operational and sleep mode. Monitoring Microcontroller Supply and Watchdog During Operation and Sleep Monitoring Microcontroller Supply and Watchdog During Operation and Sleep Design Requirements Design Parameters PARAMETER DESIGN REQUIREMENT DESIGN RESULT Voltage Threshold Typical Voltage Threshold of 1.65 V Typical Voltage Threshold of 1.65 V Window Close Time During Operation Typical tWC of 50 ms during opertation Typical tWC of 50 ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50 ms Window Open Time During Sleep Typical tWO of 12 s during operation Typical tWO of 12.75 s RESET Delay 200 ms 200 ms Output Logic Open-drain Open-drain Maximum Device Current Consumption 20 μA 250 nA typical, 3 μA maximum Design Requirements Design Parameters PARAMETER DESIGN REQUIREMENT DESIGN RESULT Voltage Threshold Typical Voltage Threshold of 1.65 V Typical Voltage Threshold of 1.65 V Window Close Time During Operation Typical tWC of 50 ms during opertation Typical tWC of 50 ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50 ms Window Open Time During Sleep Typical tWO of 12 s during operation Typical tWO of 12.75 s RESET Delay 200 ms 200 ms Output Logic Open-drain Open-drain Maximum Device Current Consumption 20 μA 250 nA typical, 3 μA maximum Design Parameters PARAMETER DESIGN REQUIREMENT DESIGN RESULT Voltage Threshold Typical Voltage Threshold of 1.65 V Typical Voltage Threshold of 1.65 V Window Close Time During Operation Typical tWC of 50 ms during opertation Typical tWC of 50 ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50 ms Window Open Time During Sleep Typical tWO of 12 s during operation Typical tWO of 12.75 s RESET Delay 200 ms 200 ms Output Logic Open-drain Open-drain Maximum Device Current Consumption 20 μA 250 nA typical, 3 μA maximum Design Parameters PARAMETER DESIGN REQUIREMENT DESIGN RESULT Voltage Threshold Typical Voltage Threshold of 1.65 V Typical Voltage Threshold of 1.65 V Window Close Time During Operation Typical tWC of 50 ms during opertation Typical tWC of 50 ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50 ms Window Open Time During Sleep Typical tWO of 12 s during operation Typical tWO of 12.75 s RESET Delay 200 ms 200 ms Output Logic Open-drain Open-drain Maximum Device Current Consumption 20 μA 250 nA typical, 3 μA maximum Design Parameters PARAMETER DESIGN REQUIREMENT DESIGN RESULT Voltage Threshold Typical Voltage Threshold of 1.65 V Typical Voltage Threshold of 1.65 V Window Close Time During Operation Typical tWC of 50 ms during opertation Typical tWC of 50 ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50 ms Window Open Time During Sleep Typical tWO of 12 s during operation Typical tWO of 12.75 s RESET Delay 200 ms 200 ms Output Logic Open-drain Open-drain Maximum Device Current Consumption 20 μA 250 nA typical, 3 μA maximum PARAMETER DESIGN REQUIREMENT DESIGN RESULT PARAMETER DESIGN REQUIREMENT DESIGN RESULT PARAMETER DESIGN REQUIREMENT DESIGN REQUIREMENT DESIGN RESULT DESIGN RESULT Voltage Threshold Typical Voltage Threshold of 1.65 V Typical Voltage Threshold of 1.65 V Window Close Time During Operation Typical tWC of 50 ms during opertation Typical tWC of 50 ms Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50 ms Window Open Time During Sleep Typical tWO of 12 s during operation Typical tWO of 12.75 s RESET Delay 200 ms 200 ms Output Logic Open-drain Open-drain Maximum Device Current Consumption 20 μA 250 nA typical, 3 μA maximum Voltage Threshold Typical Voltage Threshold of 1.65 V Typical Voltage Threshold of 1.65 V Voltage Threshold Voltage Threshold Typical Voltage Threshold of 1.65 V Typical Voltage Threshold of 1.65 V Typical Voltage Threshold of 1.65 V Typical Voltage Threshold of 1.65 V Window Close Time During Operation Typical tWC of 50 ms during opertation Typical tWC of 50 ms Window Close Time During Operation Window Close Time During Operation Typical tWC of 50 ms during opertation Typical tWC of 50 ms during opertationWC Typical tWC of 50 ms Typical tWC of 50 msWC Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.55 s Window Open Time During Operation Window Open Time During Operation Typical tWO of 1.4 s during operation Typical tWO of 1.4 s during operationWO Typical tWO of 1.55 s Typical tWO of 1.55 sWO Window Close Time During Sleep Typical tWC of 50 ms during sleep Typical tWC of 50 ms Window Close Time During Sleep Window Close Time During SleepTypical tWC of 50 ms during sleepWCTypical tWC of 50 msWC Window Open Time During Sleep Typical tWO of 12 s during operation Typical tWO of 12.75 s Window Open Time During Sleep Window Open Time During SleepTypical tWO of 12 s during operationWOTypical tWO of 12.75 sWO RESET Delay 200 ms 200 ms RESET Delay RESET Delay 200 ms 200 ms 200 ms 200 ms Output Logic Open-drain Open-drain Output Logic Output Logic Open-drain Open-drain Open-drain Open-drain Maximum Device Current Consumption 20 μA 250 nA typical, 3 μA maximum Maximum Device Current Consumption Maximum Device Current Consumption 20 μA 20 μA 250 nA typical, 3 μA maximum 250 nA typical, 3 μA maximum Detailed Design Procedure Setting Voltage Threshold The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number. OPN "Threshold Voltage" number = (VIT- - 1) / 0.05 In this example, the nominal supply voltage for the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the device is reset just before the supply voltage reaches the minimum allowed. Thus a 1.65 V threshold is chosen and, using #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB, the part number is reduced to TPS36xx13xxxxxxxQ1. The hysteresis is 5% typical, resulting in a positive-going threshold voltage, VIT+, of 1.73 V. Determining Window Timings During Operation and Sleep Modes The TPS36-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a minimum watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS36xx13FExDDFRQ1. Meeting the Minimum Reset Delay The TPS36-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS36-Q1 supports only fixed watchdog timings and fixed reset delays or programmable watchdog timings and programmable reset delays. The application requires a 200 ms minimum reset delay, thus reset delay option G is used. Because of these requirements and no need for a startup delay, the TPS36CA13FEGDDFRQ1 is used. Setting the Watchdog Window In this application, the watchdog timing options are based on the WDI signal that is provided to the TPS36-Q1. A watchdog WDI setting must be chosen such that a transition must always occur within the open watchdog window. There are several ways to achieve these window parameters. An external capacitor can be placed on the CWD pin and calculated to have a sufficient window close time. Another option is to use one of the factory-programmed timing options. An additional advantage of choosing one of the factory-programmed options is the ability to reduce the number of components required, thus reducing overall BOM cost. Calculating the RESET Pullup Resistor The TPS36-Q1 uses an open-drain configuration for the RESET output, as shown in .When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted. Open-Drain RESET Configuration Detailed Design Procedure Setting Voltage Threshold The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number. OPN "Threshold Voltage" number = (VIT- - 1) / 0.05 In this example, the nominal supply voltage for the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the device is reset just before the supply voltage reaches the minimum allowed. Thus a 1.65 V threshold is chosen and, using #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB, the part number is reduced to TPS36xx13xxxxxxxQ1. The hysteresis is 5% typical, resulting in a positive-going threshold voltage, VIT+, of 1.73 V. Setting Voltage Threshold The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number. OPN "Threshold Voltage" number = (VIT- - 1) / 0.05 In this example, the nominal supply voltage for the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the device is reset just before the supply voltage reaches the minimum allowed. Thus a 1.65 V threshold is chosen and, using #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB, the part number is reduced to TPS36xx13xxxxxxxQ1. The hysteresis is 5% typical, resulting in a positive-going threshold voltage, VIT+, of 1.73 V. The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number. OPN "Threshold Voltage" number = (VIT- - 1) / 0.05 In this example, the nominal supply voltage for the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the device is reset just before the supply voltage reaches the minimum allowed. Thus a 1.65 V threshold is chosen and, using #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB, the part number is reduced to TPS36xx13xxxxxxxQ1. The hysteresis is 5% typical, resulting in a positive-going threshold voltage, VIT+, of 1.73 V. The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number.IT-#GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB OPN "Threshold Voltage" number = (VIT- - 1) / 0.05 OPN "Threshold Voltage" number = (VIT- - 1) / 0.05IT-In this example, the nominal supply voltage for the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the device is reset just before the supply voltage reaches the minimum allowed. Thus a 1.65 V threshold is chosen and, using #GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTB, the part number is reduced to TPS36xx13xxxxxxxQ1. The hysteresis is 5% typical, resulting in a positive-going threshold voltage, VIT+, of 1.73 V.#GUID-6C90B256-3A47-4AA0-878A-A3AC84C87BCA/EQUATION-BLOCK_XV1_5Z1_YTBIT+ Determining Window Timings During Operation and Sleep Modes The TPS36-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a minimum watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS36xx13FExDDFRQ1. Determining Window Timings During Operation and Sleep Modes The TPS36-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a minimum watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS36xx13FExDDFRQ1. The TPS36-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a minimum watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS36xx13FExDDFRQ1. The TPS36-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application requires a minimum watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the possible variant options are narrowed to TPS36xx13FExDDFRQ1.TPS36-Q1WCWCWOWO Meeting the Minimum Reset Delay The TPS36-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS36-Q1 supports only fixed watchdog timings and fixed reset delays or programmable watchdog timings and programmable reset delays. The application requires a 200 ms minimum reset delay, thus reset delay option G is used. Because of these requirements and no need for a startup delay, the TPS36CA13FEGDDFRQ1 is used. Meeting the Minimum Reset Delay The TPS36-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS36-Q1 supports only fixed watchdog timings and fixed reset delays or programmable watchdog timings and programmable reset delays. The application requires a 200 ms minimum reset delay, thus reset delay option G is used. Because of these requirements and no need for a startup delay, the TPS36CA13FEGDDFRQ1 is used. The TPS36-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS36-Q1 supports only fixed watchdog timings and fixed reset delays or programmable watchdog timings and programmable reset delays. The application requires a 200 ms minimum reset delay, thus reset delay option G is used. Because of these requirements and no need for a startup delay, the TPS36CA13FEGDDFRQ1 is used. The TPS36-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays. The TPS36-Q1 supports only fixed watchdog timings and fixed reset delays or programmable watchdog timings and programmable reset delays. The application requires a 200 ms minimum reset delay, thus reset delay option G is used. Because of these requirements and no need for a startup delay, the TPS36CA13FEGDDFRQ1 is used.TPS36-Q1 Setting the Watchdog Window In this application, the watchdog timing options are based on the WDI signal that is provided to the TPS36-Q1. A watchdog WDI setting must be chosen such that a transition must always occur within the open watchdog window. There are several ways to achieve these window parameters. An external capacitor can be placed on the CWD pin and calculated to have a sufficient window close time. Another option is to use one of the factory-programmed timing options. An additional advantage of choosing one of the factory-programmed options is the ability to reduce the number of components required, thus reducing overall BOM cost. Setting the Watchdog Window In this application, the watchdog timing options are based on the WDI signal that is provided to the TPS36-Q1. A watchdog WDI setting must be chosen such that a transition must always occur within the open watchdog window. There are several ways to achieve these window parameters. An external capacitor can be placed on the CWD pin and calculated to have a sufficient window close time. Another option is to use one of the factory-programmed timing options. An additional advantage of choosing one of the factory-programmed options is the ability to reduce the number of components required, thus reducing overall BOM cost. In this application, the watchdog timing options are based on the WDI signal that is provided to the TPS36-Q1. A watchdog WDI setting must be chosen such that a transition must always occur within the open watchdog window. There are several ways to achieve these window parameters. An external capacitor can be placed on the CWD pin and calculated to have a sufficient window close time. Another option is to use one of the factory-programmed timing options. An additional advantage of choosing one of the factory-programmed options is the ability to reduce the number of components required, thus reducing overall BOM cost. In this application, the watchdog timing options are based on the WDI signal that is provided to the TPS36-Q1. A watchdog WDI setting must be chosen such that a transition must always occur within the open watchdog window. There are several ways to achieve these window parameters. An external capacitor can be placed on the CWD pin and calculated to have a sufficient window close time. Another option is to use one of the factory-programmed timing options. An additional advantage of choosing one of the factory-programmed options is the ability to reduce the number of components required, thus reducing overall BOM cost.TPS36-Q1 Calculating the RESET Pullup Resistor The TPS36-Q1 uses an open-drain configuration for the RESET output, as shown in .When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted. Open-Drain RESET Configuration Calculating the RESET Pullup ResistorRESET The TPS36-Q1 uses an open-drain configuration for the RESET output, as shown in .When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted. Open-Drain RESET Configuration The TPS36-Q1 uses an open-drain configuration for the RESET output, as shown in .When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted. Open-Drain RESET Configuration The TPS36-Q1 uses an open-drain configuration for the RESET output, as shown in .When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted.TPS36-Q1RESETOLPURESETRSTOLOLRSTDDDDPUDDRSTRESET Open-Drain RESET Configuration Open-Drain RESET Configuration Open-Drain RESET ConfigurationRESET Power Supply Recommendations This device is designed to operate from an input supply with a voltage range between 1.04 V and 6 V. An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. Power Supply Recommendations This device is designed to operate from an input supply with a voltage range between 1.04 V and 6 V. An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. This device is designed to operate from an input supply with a voltage range between 1.04 V and 6 V. An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. This device is designed to operate from an input supply with a voltage range between 1.04 V and 6 V. An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. Layout Layout Guidelines Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected. Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin. Place CCRST capacitor as close as possible to the CRST pin. Place CCWD capacitor as close as possible to the CWD pin. Place the pullup resistor on the RESET pin as close to the pin as possible. Layout Example Typical Layout for the pinout C of TPS36-Q1 Layout Layout Guidelines Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected. Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin. Place CCRST capacitor as close as possible to the CRST pin. Place CCWD capacitor as close as possible to the CWD pin. Place the pullup resistor on the RESET pin as close to the pin as possible. Layout Guidelines Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected. Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin. Place CCRST capacitor as close as possible to the CRST pin. Place CCWD capacitor as close as possible to the CWD pin. Place the pullup resistor on the RESET pin as close to the pin as possible. Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected. Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin. Place CCRST capacitor as close as possible to the CRST pin. Place CCWD capacitor as close as possible to the CWD pin. Place the pullup resistor on the RESET pin as close to the pin as possible. Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected. Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin. Place CCRST capacitor as close as possible to the CRST pin. Place CCWD capacitor as close as possible to the CWD pin. Place the pullup resistor on the RESET pin as close to the pin as possible. RESET RESET Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin. Place CCRST capacitor as close as possible to the CRST pin. Place CCWD capacitor as close as possible to the CWD pin. Place the pullup resistor on the RESET pin as close to the pin as possible. Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin.Place CCRST capacitor as close as possible to the CRST pin.CRSTPlace CCWD capacitor as close as possible to the CWD pin.CWDPlace the pullup resistor on the RESET pin as close to the pin as possible. RESET RESET Layout Example Typical Layout for the pinout C of TPS36-Q1 Layout Example Typical Layout for the pinout C of TPS36-Q1 Typical Layout for the pinout C of TPS36-Q1 Typical Layout for the pinout C of TPS36-Q1 Typical Layout for the pinout C of TPS36-Q1 TPS36-Q1 Device and Documentation Support ドキュメントの更新通知を受け取る方法 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。 サポート・リソース TI E2E サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 リンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。 Trademarks 静電気放電に関する注意事項 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 用語集 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 Device and Documentation Support ドキュメントの更新通知を受け取る方法 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。 ドキュメントの更新通知を受け取る方法 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。 ドキュメントの更新についての通知を受け取るには、ti.com のデバイス製品フォルダを開いてください。「更新の通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。ti.com サポート・リソース TI E2E サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 リンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。 サポート・リソース TI E2E サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 リンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。 TI E2E サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 TI E2E サポート ・フォーラムTI E2Eリンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。使用条件 Trademarks Trademarks 静電気放電に関する注意事項 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 静電気放電に関する注意事項 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 用語集 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 用語集 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 テキサス・インスツルメンツ用語集 テキサス・インスツルメンツ用語集この用語集には、用語や略語の一覧および定義が記載されています。 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. 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For browser-based versions of this data sheet, refer to the left-hand navigation. 重要なお知らせと免責事項 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 重要なお知らせと免責事項 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。TI の販売条件ti.com お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated Copyright © 2023, Texas Instruments Incorporated を参照してください。他のオプションの詳細と提供状況については、TI の販売代理店または TI の E2E フォーラム にお問い合わせください。

GUID-20210706-CA0I-JFBX-QVCV-D7DBHXF1456G-low.svg図 5-1 デバイスの命名規則

TPS36-Q1 表 5-1 に示すように、さまざまな機能セットを提供するピン互換デバイス・ファミリに属します。

表 5-1 ピン互換デバイス・ファミリ
デバイス電圧監視ウォッチドッグのタイプ
TPS35-Q1ありタイムアウト
TPS36-Q1ありウィンドウ
TPS3435-Q1なしタイムアウト
TPS3436-Q1なしウィンドウ