JAJSLC2C march   2014  – march 2021 TPS3700-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Inputs (INA+, INB–)
      2. 7.3.2 Outputs (OUTA, OUTB)
      3. 7.3.3 Window Voltage Detector
      4. 7.3.4 Immunity to Input Terminal Voltage Transients
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 VPULLUP to a Voltage Other Than VDD
      2. 8.1.2 Monitoring VDD
      3. 8.1.3 Monitoring a Voltage Other Than VDD
      4. 8.1.4 Monitoring Overvoltage and Undervoltage for Separate Rails
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Supply Capacitor
        2. 8.2.1.2 Input Capacitors
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2 Detailed Design Procedure

Use Equation 1 through Equation 4 to calculate the resistor divider values and target threshold voltage.

Equation 1. RT = R1 + R2 + R3

Select a value for RT such that the current through the divider is approximately 100-times higher than the input current at the INA+ and INB– terminals. The resistors can have high values to minimize current consumption as a result of low-input bias current without adding significant error to the resistive divider. See the application note Optimizing Resistor Dividers at a Comparator Input (SLVA450) for details on sizing input resistors.

Use Equation 2 to calculate the value of R3.

Equation 2. GUID-917231C3-0CB3-40D2-B483-06B633E861E8-low.gif

where

  • VMON(OV) is the target voltage at which an overvoltage condition is detected

Use Equation 3 or Equation 4 to calculate the value of R2.

Equation 3. GUID-45A1E6DB-088B-431D-8CEF-942E38F8DAE3-low.gif

where

  • VMON(no UV) is the target voltage at which an undervoltage condition is removed as VMON rises
Equation 4. GUID-E401BE1F-1362-474E-B861-5C900671B08E-low.gif

where:

VMON(UV) is the target voltage at which an undervoltage condition is detected