JAJSLC2C
march 2014 – march 2021
TPS3700-Q1
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Timing Diagram
6.8
Switching Characteristics
6.9
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Inputs (INA+, INB–)
7.3.2
Outputs (OUTA, OUTB)
7.3.3
Window Voltage Detector
7.3.4
Immunity to Input Terminal Voltage Transients
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.1.1
VPULLUP to a Voltage Other Than VDD
8.1.2
Monitoring VDD
8.1.3
Monitoring a Voltage Other Than VDD
8.1.4
Monitoring Overvoltage and Undervoltage for Separate Rails
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Input Supply Capacitor
8.2.1.2
Input Capacitors
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Trademarks
11.3
静電気放電に関する注意事項
11.4
用語集
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DDC|6
MPDS124I
DSE|6
MPDS287A
サーマルパッド・メカニカル・データ
発注情報
jajslc2c_oa
jajslc2c_pm
8.2
Typical Application
Figure 8-5
Typical Application Schematic