JAJSFN5C November   2014  – February 2019 TPS3701

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
      2.      標準的な誤差と接合部温度との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Inputs (INA, INB)
      2. 7.3.2 Outputs (OUTA, OUTB)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > UVLO)
      2. 7.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
      3. 7.4.3 Power-On-Reset (VDD < V(POR))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Window Voltage Detector Considerations
      2. 8.1.2 Input and Output Configurations
      3. 8.1.3 Immunity to Input Pin Voltage Transients
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over the operating temperature range of TJ = –40°C to +125°C, 1.8 V ≤ VDD < 36 V, and pull-up resistors RP1,2 = 100 kΩ, unless otherwise noted. Typical values are at TJ = 25°C and VDD = 12 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Supply voltage range 1.8 36 V
V(POR) Power-on reset voltage(1) VOL ≤ 0.2 V 0.8 V
VIT–(INA) INA pin negative input threshold voltage VDD = 1.8 V to 36 V 397 400 403 mV
VIT+(INA) INA pin positive input threshold voltage VDD = 1.8 V to 36 V 400 405.5 413 mV
VHYS(INA) INA pin hysteresis voltage
(HYS = VIT+(INA) – VIT–(INA))		 2 5.5 12 mV
VIT–(INB) INB pin negative input threshold voltage VDD = 1.8 V to 36 V 387 394.5 400 mV
VIT+(INB) INB pin positive input threshold voltage VDD = 1.8 V to 36 V 397 400 403 mV
VHYS(INB) INB pin hysteresis voltage
(HYS = VIT+(INB) – VIT–(INB))		 2 5.2 12 mV
VOL Low-level output voltage VDD = 1.8 V, IOUT = 3 mA 130 250 mV
VDD = 5 V, IOUT = 5 mA 150 250 mV
IIN Input current (at INA, INB pins) VDD = 1.8 V and 36 V, VINA, VINB = 6.5 V –25 +1 +25 nA
VDD = 1.8 V and 36 V, VINA, VINB = 0.1 V –15 +1 +15 nA
ID(leak) Open-drain output leakage current VDD = 1.8 V and 36 V, VOUT = 25 V 10 300 nA
IDD Supply current VDD = 1.8 V – 36 V 8 11 µA
UVLO Undervoltage lockout(2) VDD falling 1.3 1.5 1.7 V
(1) The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. If less than V(POR), the output is undetermined.
(2) When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined if less than V(POR).