In a typical TPS3702 application, the outputs are connected to a reset or enable input of a processor [such as a digital signal processor (DSP), application-specific integrated circuit (ASIC), or other processor type] or the outputs are connected to the enable input of a voltage regulator [such as a dc-dc converter or low-dropout regulator (LDO)].

The TPS3702 provides two open-drain outputs (UV and OV) and uses pull-up resistors to hold these lines high when the output goes to a high-impedance state. Connect the pull-up resistors to the proper voltage rails to enable the outputs to be connected to other devices at the correct interface voltage levels. The TPS3702 outputs can be pulled up to 18V, independent of the device supply voltage. To make sure of proper voltage levels, give some consideration when choosing the pull-up resistor values. The pull-up resistor value is determined by V_OL, output capacitive loading, and output leakage current (I_D(leak)). These values are specified in the Section 5.5 table. Use wired-OR logic to merge the undervoltage and overvoltage signals into one logic signal that goes low if either outputs are asserted because of a fault condition.

Table 6-1 describes how the outputs are either asserted low or high impedance. See Figure 5-1 for a timing diagram that describes the relationship between the threshold voltages and the respective output.