JAJSGG5D November   2018  – March 2021 TPS3703-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD
      2. 8.3.2 SENSE
      3. 8.3.3 RESET
      4. 8.3.4 Capacitor Time (CT)
      5. 8.3.5 Manual Reset ( MR)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(MIN))
      2. 8.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)
      3. 8.4.3 Power-On Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Voltage Threshold Accuracy
      2. 9.1.2 CT Reset Time Delay
        1. 9.1.2.1 Factory-Programmed Reset Delay Timing
        2. 9.1.2.2 Programmable Reset Delay-Timing
      3. 9.1.3 RESET Latch Mode
      4. 9.1.4 Adjustable Voltage Thresholds
      5. 9.1.5 Immunity to SENSE Pin Voltage Transients
        1. 9.1.5.1 Hysteresis
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2: RESET Latch Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Evaluation Module
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

At 1.7 V ≤ VDD ≤ 5.5 V, CT = MR =  Open, RESET Voltage (VRESET) = 10 kΩ to VDD, RESET load = 10 pF, and over the operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical conditions at VDD = 3.3 V.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VDDSupply voltage1.75.5V
UVLOUnder voltage lockout(3)VDD falling below 1.7 V1.21.7V
VPORPower on reset voltage(2)VOL(max) = 0.25 V, IOUT = 15 µA1V
VIT+(OV)Positive- going threshold accuracy–0.7±0.250.7%
VIT-(UV)Negative-going threshold accuracy–0.7±0.250.7%
VHYSHysteresis voltage(1)0.30.550.8%
IDDSupply currentVDD ≤ 5.5 V4.57µA
ISENSEInput current, SENSE pinVSENSE = 5 V11.5µA
VOLLow level output voltageVDD = 1.7 V, IOUT = 0.4 mA250mV
VDD = 2 V, IOUT = 3 mA250mV
VDD = 5 V, IOUT = 5 mA250mV
ILKGOpen drain output leakage currentVDD = VRESET  = 5.5 V300nA
VMR_LMR logic low input0.3V
VMR_HMR logic high input1.4V
VCT_HHigh level CT pin voltage1.4V
RMRManual reset Internal pullup resistance100KΩ
ICTCT pin charge current337375413nA
VCTCT pin comparator threshold voltage(4)1.1331.151.167V
(1) Hysteresis is with respect of the tripoint (VIT-(UV), VIT+(OV)).
(2) VPOR is the minimum VDD voltage level for a controlled output state.
(3) RESET pin is driven low when VDD falls below UVLO.
(4) VCT voltage refers to the comparator threshold voltage that measures the voltage level of the external capacitor at CT pin.