JAJSGG5D November   2018  – March 2021 TPS3703-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD
      2. 8.3.2 SENSE
      3. 8.3.3 RESET
      4. 8.3.4 Capacitor Time (CT)
      5. 8.3.5 Manual Reset ( MR)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(MIN))
      2. 8.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)
      3. 8.4.3 Power-On Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Voltage Threshold Accuracy
      2. 9.1.2 CT Reset Time Delay
        1. 9.1.2.1 Factory-Programmed Reset Delay Timing
        2. 9.1.2.2 Programmable Reset Delay-Timing
      3. 9.1.3 RESET Latch Mode
      4. 9.1.4 Adjustable Voltage Thresholds
      5. 9.1.5 Immunity to SENSE Pin Voltage Transients
        1. 9.1.5.1 Hysteresis
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2: RESET Latch Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Evaluation Module
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Timing Requirements

At 1.7 V ≤ VDD ≤ 5.5 V, CT = MR =  Open, RESET Voltage (VRESET) = 10 kΩ to VDD, RESET load = 10 pF, and over the operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical conditions at VDD = 3.3 V.
MIN NOM MAX UNIT
tD Reset time delay, TPS3703A, TPS3703E CT = Open 7 10 13 ms
Reset time delay, TPS3703A, TPS3703E CT = 10 kΩ to VDD 140 200 260
Reset time delay, TPS3703B, TPS3703F CT = Open 0.7 1 1.3
Reset time delay, TPS3703B, TPS3703F CT = 10 kΩ to VDD 14 20 26
Reset time delay, TPS3703C, TPS3703G CT = Open 3.5 5 6.5
Reset time delay, TPS3703C, TPS3703G CT = 10 kΩ to VDD 70 100 130
Reset time delay, TPS3703D, TPS3703H CT = 10 kΩ to VDD
CT = Open		 50 µs
tPD Propagation detect delay(1)(2) 15 30 µs
tR Output rise time(1)(3) 2.2 µs
tF Output fall time(1)(3) 0.2 µs
tSD Startup delay(4) 300 µs
tGI (VIT-) Glitch Immunity undervoltage VIT-(UV), 5% Overdrive(1) 3.5 µs
tGI (VIT+) Glitch Immunity overvoltage VIT+(OV), 5% Overdrive(1) 3.5 µs
tGI ( MR) Glitch Immunity MR pin 25 ns
tPD ( MR) Propagation delay from MR low to assert RESET 500 ns
tMR_W MR pin pulse width duration to assert RESET 1 µs
tD ( MR) MR reset time delay  tD ms
(1) 5% Overdrive from threshold. Overdrive % = [VSENSE - VIT] / VIT; Where VIT stands for VIT-(UV) or VIT+(OV)
(2) tPD measured from threhold trip point (VIT-(UV) or VIT+(OV)) to RESET VOL voltage
(3) Output transitions from VOL to 90% for rise times and 90% to VOL for fall times.
(4) During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD + tD before the output is in the correct state.