SNVSCN2 September   2024 TPS37100-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 7.3.1.2 Power-On Reset (VDD < VPOR )
      2. 7.3.2 SENSE
        1. 7.3.2.1 Adjustable Voltage Thresholds
        2. 7.3.2.2 SENSE Hysteresis
        3. 7.3.2.3 Reverse Polarity Protection
      3. 7.3.3 Output Logic Configurations
        1. 7.3.3.1 Open-Drain
        2. 7.3.3.2 Active-Low (OUT A and OUT B)
        3. 7.3.3.3 Latching
      4. 7.3.4 User-Programmable Release Time Delay
        1. 7.3.4.1 Deassertion Time Delay Configuration
      5. 7.3.5 User-Programmable Sense Delay
        1. 7.3.5.1 Sense Time Delay Configuration
      6. 7.3.6 Analog Out
      7. 7.3.7 Built-in Self-Test
        1. 7.3.7.1 Latching
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Off-Battery Monitoring
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Dissipation and Device Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Creepage Distance
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

At VDD(MIN) ≤ VDD ≤ VDD(MAX), CTR = CTS = open, output OUT A and OUT B pull-up resistor with RPU = 10kΩ and VPU = 5.5V. The operating free-air temperature range TA = -40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 16V. VIT refers to VITN or VITP. AOUT CLoad = 100nF and AOUT VOUT = 2.5V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD
VDD Supply Voltage 3 105 V
UVLO (1) Undervoltage Lockout VDD Falling below VDD (MIN) 2.6 V
UVLO(HYS) (1) Undervoltage Lockout Hysteresis VDD Rising above VDD (MIN) 400 mV
VPOR Power on Reset Voltage (2)
OUT_A 		VOL(MAX) = 300mV
IOUT A(Sink) = 15µA
 1.4 V
VPOR Power on Reset Voltage (2)
OUT_B 		VOL(MAX) = 300mV
IOUT B (Sink) = 15µA
 1.4 V
IDD Supply current into VDD pin
VDD (MIN) ≤ VDD ≤ VDD (MAX)
Analog out = disabled
 5 13 µA
IDD Supply current into VDD pin VDD (MIN) ≤ VDD ≤ VDD (MAX)

Analog out = enabled
IAOUT = 0µA		 9 18 µA
SENSE (Input)
ISENSE Input current VIT = 800mV
 250 nA
ISENSE Input current VIT = 3 V to 105 V
 1.5 8 µA
VITN Input Threshold Negative
(Undervoltage)		 VITN = 3V to 105V -1.1 1.1 %
VITN = 800mV -0.8 0.8 %
VITP Input Threshold Positive 
(Overvoltage)		 VITP = 3V to 105V -1.1 1.1 %
VITP = 800mV -0.8 0.8 %
VHYS Hysteresis Accuracy (3) VHYS Range = 1% 0.8 1 1.2 %
VHYS Hysteresis Accuracy (3) VHYS Range = 2% 1.5 2 2.5 %
VHYS Hysteresis Accuracy (3) VHYS Range = 5% 4.5 5 6 %
VHYS Hysteresis Accuracy (3) VHYS Range = 10% 9 10 11 %
OUT A and OUT B (Output)
Ilkg(OUT A) Open-Drain leakage VOUT A = 5.5V
VITN < VSENSE < VITP		 900 nA
VOUT A = 105V
VITN < VSENSE < VITP		 900 nA
VOL(OUT A) Low level output voltage 3V ≤ VDD ≤ 105V
IOUT A = 2.7 mA
 350 mV
Ilkg(OUT B) Open-Drain leakage VOUT B = 5.5V
VITN < VSENSE < VITP		 300 nA
VOL(OUT B) Low level output voltage 3V ≤ VDD ≤ 105V
IOUT B = 5 mA
 300 mV
Capacitor Timing (CTS, CTR)
RCTR Internal resistance (CTR) 2880 3600 4320 Kohm
RCTS Internal resistance (CTS) 2880 3600 4320 Kohm
Analog Out
COUT Output buffer capacitor for stability ESR = 5m to 20m Ohm 0.07 0.1 0.13 µF
IOUT Output buffer current, sink & source -20 +20 µA
ISC Short circuit current. 450 µA
Slew Rate Slew Rate for current 50 mA/ms
VIL_EN 500 mV
VIH_EN 1300 mV
VCM Vout Range VDD + VDO < 5V 0.35 VDD-VDO V
VCM Vout Range VDD + VDO ≥ 5V 0.35 5 V
VDO Voltage dropout IAOUT = 0µA 0.41 V
VDO Voltage dropout IAOUT = 20µA 0.41 V
Accuracy 25℃ IAOUT = 0µA, TA = 25℃
Analog Out Scale = 0.75, 8 to 58		 -0.2 0.2 %
Accuracy over Temp IAOUT = 0µA, TA = -40℃ to 125℃
Analog Out Scale = 8 to 58
3V > VAOUT > 0.5V		 -1 1 %
Accuracy over Temp IAOUT = 0µA, TA = -40℃ to 125℃
Analog Out Scale = 8 to 58
0.5V > VAOUT		 -2 2 %
Accuracy over Temp IAOUT = 0µA, TA = -40℃ to 125℃
Analog Out Scale = 0.75
3V > VOUT > 0.5V		 -1 1 %
Accuracy over Temp IAOUT = 0µA, TA = -40℃ to 125℃
Analog Out Scale = 0.75
0.5V > VAOUT		 -2 2 %
Line Regulation VDD = 3V to 105V -0.1 0.1 %
Load Regulation (source) Iload = 0µA to 20µA 0.01 %/µA
Load Regulation (sink) IAOUT = 0µA to -20µA 0.01 %/µA
Turn-on (EN) Time IAOUT = 0µA, Vout = Sense with scaling within 0.7% 5.1 ms
Response time VAOUT < 0.7% accuracy,  90% of input to 0.7% accuracy of output 5 ms
Ilkg(BIST_OD) Open-Drain leakage VBIST = 5.5V
VITN < VSENSE < VITP		 300 nA
VBIST_OL Low level output voltage 3V ≤ VDD ≤ 105V
IBIST (Sink) = 5mA
 300 mV
VBIST_EN BIST_EN pin logic low input 500 mV
VBIST_EN BIST_EN pin logic high input 1300 mV
(1) When VDD voltage falls below UVLO, OUT A and OUT B are asserted until VPOR. VDD slew rate ≤ 1V / µs
(2) VPOR is the minimum VDD voltage for a controlled output state. Below VPOR, the output cannot be determined. VDD dv/dt ≤ 1V/µs
(3) Hysteresis is with respect to VITP and VITN voltage threshold. VITP has negative hysteresis and VITN has positive hysteresis.