JAJSKP3E August   2020  – August 2023 TPS38-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 8.3.1.2 Power-On Reset (VDD < VPOR )
      2. 8.3.2 SENSE
        1. 8.3.2.1 SENSE Hysteresis
      3. 8.3.3 Output Logic Configurations
        1. 8.3.3.1 Open-Drain
        2. 8.3.3.2 Push-Pull
        3. 8.3.3.3 Active-High (RESET)
        4. 8.3.3.4 Active-Low (RESET)
      4. 8.3.4 User-Programmable Reset Time Delay
        1. 8.3.4.1 Reset Time Delay Configuration
      5. 8.3.5 User-Programmable Sense Delay
        1. 8.3.5.1 Sense Time Delay Configuration
      6. 8.3.6 Manual RESET (CTR1 / MR) and (CTR2 / MR) Input
      7. 8.3.7 Adjustable Voltage Thresholds
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Adjustable Voltage Thresholds
    2. 9.2 Application Information
    3. 9.3 Typical Application
      1. 9.3.1 Design 1: Automotive Off-Battery Monitoring
        1. 9.3.1.1 Design Requirements
        2. 9.3.1.2 Detailed Design Procedure
        3. 9.3.1.3 Application Curves
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Power Dissipation and Device Operation
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Creepage Distance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.4.1 Reset Time Delay Configuration

The time delay (tCTR) can be programmed by connecting a capacitor between CTR1 pin and GND, CTR2 for channel 2. In this section CTRx represent either channel 1 or channel 2.

The relationship between external capacitor CCTRx_EXT (typ) and the time delay tCTRx (typ) is given by Equation 1.

Equation 1. tCTRx (typ) = -ln (0.28) x RCTRx (typ) x CCTRx_EXT (typ) + tCTRx (no cap)

RCTRx (typ) = is in kilo ohms (kOhms)

CCTRx_EXT (typ) = is given in microfarads (μF)

tCTRx (typ) = is the reset time delay in (ms)

The reset delay varies according to three variables: the external capacitor (CCTRx_EXT), CTR pin internal resistance (RCTRx) provided in Section 7.5, and a constant. The minimum and maximum variance due to the constant is show in Equation 5 and Equation 6:

Equation 2. tCTRx (min) = -ln (0.31) x RCTRx (min) x CCTRx_EXT (min) + tCTRx (no cap (min))
Equation 3. tCTRx (max) = -ln (0.25) x RCTRx (max) x CCTRx_EXT (max) + tCTRx (no cap (max))

The recommended maximum reset delay capacitor for the TPS38-Q1 is limited to 10 μF as this ensures enough time for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a capacitor value can cause very slow charge up (rise times) and system noise can cause the the internal circuit to trip earlier or later near the threshold. This leads to variation in time delay where it can make the delay accuracy worse in the presence of system noise.

When a voltage fault occurs, the previously charged up capacitor discharges and if the monitored voltage returns from the fault condition before the delay capacitor discharges completely, the delay will be shorter than expected. The capacitor will begin charging from a voltage above zero and resulting in shorter than expected time delay. A larger delay capacitor can be used so long as the capacitor has enough time to fully discharge during the duration of the voltage fault. To ensure the capacitor is fully discharged, the time period or duration of the voltage fault needs to be greater than 5% of the programmed reset time delay.