JAJSQE7A May 2023 – November 2023 TPS3808E
PRODUCTION DATA
RESET remains high (unasserted) as long as SENSE is above its threshold (VIT) and the manual reset (MR) is logic high. If either SENSE falls below VIT or MR is driven low, RESET is asserted, driving the RESET pin to a low impedance.
Once MR is again logic high and SENSE is above VIT + VHYS (the threshold hysteresis), a delay circuit is enabled that holds RESET low for a specified reset delay period. Once the reset delay has expired, the RESET pin goes to a high impedance state. The pullup resistor from the open-drain RESET to the supply line can be used to allow the reset signal for the microprocessor to have a voltage higher than VDD (up to 6 V). The pullup resistor should be no smaller than 10 kΩ as a result of the finite impedance of the RESET line.