SGLS143D December   2002  – July 2019 TPS3820-Q1 , TPS3823-Q1 , TPS3824-Q1 , TPS3825-Q1 , TPS3828-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic
      2.      Normalized Input Threshold Voltage vs Free-Air Temperature
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Manual Reset (MR)
      2. 8.3.2 Active High or Active Low Output
      3. 8.3.3 Push-Pull or Open-Drain Output
      4. 8.3.4 Watchdog Timer (WDI)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Supply Rail Monitoring with Watchdog Time-out and 200-ms Delay
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Decoupling WDI During Reset Event
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
        1. 12.1.1.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DBV|5
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating junction temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage RESET TPS382x-25-Q1 VDD = VIT− + 0.2 V, IOH = –20 μA 0.8 × VDD V
TPS382x-30-Q1
TPS382x-33-Q1		 VDD = VIT− + 0.2 V, IOH = –30 μA
TPS382x-50-Q1 VDD = VIT− + 0.2 V IOH = –120 μA VDD − 1.5 V
RESET TPS3824-25-Q1
TPS3825-25-Q1		 VDD ≥ 1.8 V, IOH = –100 μA 0.8 × VDD
TPS3824-30-Q1
TPS3825-30-Q1		 VDD ≥ 1.8 V, IOH = –150 μA
TPS3824-33-Q1
TPS3825-33-Q1
TPS3824-50-Q1
TPS3825-50-Q1
VOL Low-level output voltage RESET TPS3824-25-Q1
TPS3825-25-Q1		 VDD = VIT− + 0.2 V, IOL = 1 mA 0.4 V
TPS3824-30-Q1
TPS3825-30-Q1		 VDD = VIT− + 0.2 V, IOL = 1.2 mA
TPS3824-33-Q1
TPS3825-33-Q1
TPS3824-50-Q1
TPS3825-50-Q1		 VDD = VIT− + 0.2 V, IOL = 3 mA
RESET TPS382x-25-Q1 VDD = VIT− – 0.2 V, IOL = 1 mA 0.45
TPS382x-30-Q1 VDD = VIT− – 0.2 V, IOL = 1.2 mA
TPS382x-33-Q1
TPS382x-50-Q1 VDD = VIT− – 0.2 V, IOL = 3 mA
Power-up reset voltage(1) VDD ≥ 1.1 V, IOL = 20 μA 0.4 V
VIT− Negative-going input
threshold voltage (2) 		TPS382x-25-Q1 TA = 0°C to 85°C 2.21 2.25 2.3 V
TPS382x-30-Q1 2.59 2.63 2.69
TPS382x-33-Q1 2.88 2.93 3
TPS382x-50-Q1 4.49 4.55 4.64
TPS382x-25-Q1 TA = –40°C to 125°C 2.19 2.25 2.3
TPS382x-30-Q1 2.55 2.63 2.69
TPS382x-33-Q1 2.84 2.93 3
TPS382x-50-Q1 4.44 4.55 4.64
Vhys Hysteresis at VDD input TPS382x-25-Q1 30 mV
TPS382x-30-Q1
TPS382x-33-Q1
TPS382x-50-Q1 50
IIH(AV) Average high-level input current WDI WDI = VDD, time average (DC = 88%) 120 µA
IIL(AV) Average low-level input current WDI = 0.3 V, VDD = 5.5 V time average (DC = 12%) –15
IIH High-level input current WDI WDI = VDD 140 190 µA
MR MR = VDD × 0.7, VDD = 5.5 V –40 –60
IIL Low-level input current WDI WDI = 0.3 V, VDD = 5.5 V 140 190 µA
MR MR = 0.3 V, VDD = 5.5 V –110 –160
IOS Output short-circuit current(3) RESET TPS382x-25-Q1 VDD = VIT, max + 0.2 V, VO = 0 V –400 µA
TPS382x-30-Q1
TPS382x-33-Q1
TPS382x-50-Q1 –800
IDD Supply current WDI, MR, and outputs unconnected 15 25 µA
Internal pullup resistor at MR 52 kΩ
Ci Input capacitance at MR, WDI VI = 0 V to 5.5 V 5 pF
(1) The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 μs/V.
(2) To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 μF) should be placed near the supply terminals.
(3) The RESET short-circuit current is the maximum pullup current when RESET is driven low by a microprocessor bidirectional reset pin.