JAJSU21 April 2024 TPS3842
ADVANCE INFORMATION
RESET (active low) denoted with a bar above the pin label. RESET remains high voltage (VOH, deasserted) (open-drain variant VOH is measured against the pullup voltage) as long as sense voltage is in normal operation above the threshold boundary and VDD voltage is above VDD(min). If SENSE falls below VITN for a time period longer than tPD+tCTS, RESET is asserted, driving the RESET pin to a low impedance.
Once SENSE is above VITN + VHYS, a delay circuit (CTR) is enabled that holds RESET low for a specified reset delay period. Once the reset delay has expired, the RESET pin goes to a high impedance state.
Open-drain output requires an external pull-up resistor to hold the voltage high to the required voltage logic. Connect the pull-up resistor to the proper voltage rail to enable the output to be connected to other devices at the correct interface voltage levels. RESET is supports pull-up voltages up to 42V and is independent of VDD and SENSE voltages.
To select the right pull-up resistor, consider system VOH and the Open-Drain Leakage Current (ILKG) provided in the electrical characteristics to set the maximum pull-up resistor value. Low pull-up resistor values increase the amount of current through the internal open-drain output. The current through the open-drain output must be lower than the IRESET of the device.