JAJSU21 April   2024 TPS3842

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
  8. 7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 SENSE Input
        1. 8.3.1.1 SENSE Hysteresis
      2. 8.3.2 Selecting the SENSE Delay Time
      3. 8.3.3 Selecting the RESET Delay Time
      4. 8.3.4 RESET Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 8.4.3 Below Power-On Reset (VDD < VPOR)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Meeting the Sense and Reset Delay
      3. 9.2.3 Application Curve
      4. 9.2.4 Power Supply Recommendations
      5. 9.2.5 Layout
        1. 9.2.5.1 Layout Guidelines
        2. 9.2.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 Trademarks
    3. 10.3 静電気放電に関する注意事項
    4. 10.4 サポート・リソース
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.5.1 Layout Guidelines

  • Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a greater than 0.1µF ceramic capacitor as near as possible to the VDD pin.
  • For noisy envirionments and to improve noise immunity on the SENSE pins, an optional 1nF capacitor between the SENSE pin and GND can reduce the sensitivity to transient voltages on the monitored signal. An alternative to improve noise immunity is to use the CTS feature.
  • If a capacitor is used on CTS or CTR, place these components as close as possible to the respective pins. If the capacitor adjustable pins are left unconnected, make sure to minimize the amount of parasitic capacitance to not affect the TPD or tCTR.
  • Place the pull-up resistors on RESET as close to the pin as possible.
  • When laying out metal traces, separate high voltage traces from low voltage traces as much as possible.
  • Do not have high voltage metal pads or traces closer than 20mils (0.5mm) to the low voltage metal pads or traces.