JAJSU21A April   2024  – August 2024 TPS3842

PRODUCTION DATA  

1.   1
2. 1 特長
3. 2 アプリケーション
4. 3 概要
5. 4 Device Comparison
6. 5 Pin Configuration and Functions
7. 6 Specification
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 ESD Ratings
   3. 6.3 Recommended Operating Conditions
   4. 6.4 Thermal Information
   5. 6.5 Electrical Characteristics
   6. 6.6 Timing Requirements
   7. 6.7 Switching Characteristics
   8. 6.8 Timing Diagram
   9. 6.9 Typical Characteristics
8. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagrams
   3. 7.3 Feature Description
      1. 7.3.1 SENSE Input
         1. 7.3.1.1 SENSE Hysteresis
      2. 7.3.2 Selecting the SENSE Delay Time
      3. 7.3.3 Selecting the RESET Delay Time
      4. 7.3.4 RESET Output
   4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 7.4.3 Below Power-On Reset (VDD < VPOR)
9. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
         1. 8.2.2.1 Meeting the Sense and Reset Delay
      3. 8.2.3 Application Curve
      4. 8.2.4 Power Supply Recommendations
      5. 8.2.5 Layout
         1. 8.2.5.1 Layout Guidelines
         2. 8.2.5.2 Layout Example
10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 Trademarks
    3. 9.3 静電気放電に関する注意事項
    4. 9.4 サポート・リソース
    5. 9.5 用語集
11. 10Revision History
12. 11Mechanical, Packaging, and Orderable Information