The SENSE input provides a pin at which any system voltage can be monitored. If the voltage on this pin drops below V_ITN for a t_PD+t_CTS time interval, then RESET is asserted. The comparator has a built-in hysteresis to suppress unintended RESET assertions and de-assertions. For noisy envirionments, good analog design practice is to put a 1nF bypass capacitor on the SENSE input to reduce sensitivity to transients and layout parasitics or leaverage the CTS feature to set a minimum fault time interval before RESET is asserted.

Figure 7-3 illustrates an example of how to adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on the desired voltage threshold and device part number. TI recommends using the 700mV threshold option when using an external resistor divider. The variant bypasses the internal resistor ladder for higher accuracy when using external resistors.

For example, consider a 12V rail, V_MON, being monitored for undervoltage (UV) using of the TPS3842A011DRLR variant, as shown in Figure 7-3. The monitored UV threshold, denoted as V_MON-, is the desired voltage where the device asserts the reset. For this example V_MON- = 5.8V. To assert an undervoltage reset the voltage at the sense pin, V_SENSE, needs to be equal to the input threshold negative, V_ITN. For this example variant V_SENSE = V_ITN = 0.7V. Using R₁ and R₂ the correlation between V_MON- and V_SENSE can be seen in Equation 1. Assuming R₁ = 100kΩ, and R₂ can be calculated as R₂ = 13.7kΩ.

The TPS3842 hysteresis depends on the configuration selected. For the reset signal to become deasserted, V_MON must go above V_ITN + V_HYS. For this example variant a 1% voltage threshold hysteresis was selected. Therefore, V_MON equals 5.858V when the reset signal becomes deasserted. If a 10% hysteresis option was instead used, V_MON equals 6.38V when the reset signal becomes deasserted.

Figure 7-3 Using the TPS3842A011DRLR to Monitor a User-Defined Threshold Voltage