JAJSD46B January   2017  – September 2021 TPS3850-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 CRST
      2. 7.3.2 RESET
      3. 7.3.3 Over- and Undervoltage Fault Detection
      4. 7.3.4 Adjustable Operation Using the TPS3850H01Q1
      5. 7.3.5 Window Watchdog
        1. 7.3.5.1 SET0 and SET1
          1. 7.3.5.1.1 Enabling the Window Watchdog
          2. 7.3.5.1.2 Disabling the Watchdog Timer When Using the CRST Capacitor
          3. 7.3.5.1.3 SET0 and SET1 During Normal Watchdog Operation
      6. 7.3.6 Window Watchdog Timer
        1. 7.3.6.1 CWD
        2. 7.3.6.2 WDI Functionality
        3. 7.3.6.3 WDO Functionality
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDD is Below VPOR ( VDD < VPOR)
      2. 7.4.2 Above Power-On-Reset But Less Than UVLO (VPOR ≤ VDD < VUVLO)
      3. 7.4.3 Above UVLO But Less Than VDD (min) (VUVLO ≤ VDD < VDD (min))
      4. 7.4.4 Normal Operation (VDD ≥ VDD (min))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CRST Delay
        1. 8.1.1.1 Factory-Programmed Reset Delay Timing
        2. 8.1.1.2 Programmable Reset Delay Timing
      2. 8.1.2 CWD Functionality
        1. 8.1.2.1 Factory-Programmed Timing Options
        2. 8.1.2.2 Adjustable Capacitor Timing
        3. 8.1.2.3 45
      3. 8.1.3 Adjustable SENSE Configuration
      4. 8.1.4 Overdrive on the SENSE Pin
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Monitoring a 1.2-V Rail with Factory-Programmable Watchdog Timing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Monitoring the 1.2-V Rail
          2. 8.2.1.2.2 Meeting the Minimum Reset Delay
          3. 8.2.1.2.3 Setting the Watchdog Window
          4. 8.2.1.2.4 Calculating the RESET and WDO Pullup Resistor
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2: Using the TPS3850H01Q1 to Monitor a 0.7-V Rail With an Adjustable Window Watchdog Timing
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Meeting the Minimum Reset Delay
          2. 8.2.2.2.2 Setting the Window Watchdog
          3. 8.2.2.2.3 Watchdog Disabled During the Initialization Period
          4. 8.2.2.2.4 Calculating the Sense Resistor
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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発注情報
8.2.1.2.4 Calculating the RESET and WDO Pullup Resistor

The TPS3850-Q1 uses an open-drain configuration for the RESET circuit, as shown in Figure 8-6. When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.4 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.4 V with IRST kept below 10 mA. For this example, with a VPU of 1.8 V, a resistor must be chosen to keep IRST below 200 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET or WDO is asserted. As illustrated in Figure 6-12, the RESET current is at 180 μA and the low-level output voltage is approximately zero.

GUID-00805593-F54B-4031-84F8-C52D040EB04B-low.gifFigure 8-6 Open-Drain RESET Configuration