JAJSCT6B October   2016  – September 2021 TPS3850

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 CRST
      2. 7.3.2 RESET
      3. 7.3.3 Over- and Undervoltage Fault Detection
      4. 7.3.4 Adjustable Operation Using the TPS3850H01
      5. 7.3.5 Window Watchdog
        1. 7.3.5.1 SET0 and SET1
          1. 7.3.5.1.1 Enabling the Window Watchdog
          2. 7.3.5.1.2 Disabling the Watchdog Timer When Using the CRST Capacitor
          3. 7.3.5.1.3 SET0 and SET1 During Normal Watchdog Operation
      6. 7.3.6 Window Watchdog Timer
        1. 7.3.6.1 CWD
        2. 7.3.6.2 WDI Functionality
        3. 7.3.6.3 WDO Functionality
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDD is Below VPOR ( VDD < VPOR)
      2. 7.4.2 Above Power-On-Reset But Less Than UVLO (VPOR ≤ VDD < VUVLO)
      3. 7.4.3 Above UVLO But Less Than VDD (min) (VUVLO ≤ VDD < VDD (min))
      4. 7.4.4 Normal Operation (VDD ≥ VDD (min))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CRST Delay
        1. 8.1.1.1 Factory-Programmed Reset Delay Timing
        2. 8.1.1.2 Programmable Reset Delay-Timing
      2. 8.1.2 CWD Functionality
        1. 8.1.2.1 Factory-Programmed Timing Options
        2. 8.1.2.2 Adjustable Capacitor Timing
      3. 8.1.3 Adjustable SENSE Configuration
      4. 8.1.4 Overdrive on the SENSE Pin
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Monitoring a 1.2-V Rail with Factory-Programmable Watchdog Timing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Monitoring the 1.2-V Rail
          2. 8.2.1.2.2 Meeting the Minimum Reset Delay
          3. 8.2.1.2.3 Setting the Watchdog Window
          4. 8.2.1.2.4 Calculating the RESET and WDO Pullup Resistor
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2: Using TPS3850H01 to monitor a 0.7-V Rail With an Adjustable Window Watchdog Timing
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Meeting the Minimum Reset Delay
          2. 8.2.2.2.2 Setting the Window Watchdog
          3. 8.2.2.2.3 Watchdog Disabled During the Initialization Period
          4. 8.2.2.2.4 Calculating the Sense Resistor
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.2.2 Adjustable Capacitor Timing

Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected to CWD, then a 375-nA constant-current source charges CCWD until VCWD = 1.21 V. The TPS3850 determines the window watchdog upper boundary with the formula given in Equation 6, where CCWD is in microfarads and tWDU is in seconds.

Equation 6. tWDU(typ) = 77.4 × CCWD + 0.055

The TPS3850 is designed and tested using CCWD capacitors between 100 pF and 1 µF. Note that Equation 6 is for ideal capacitors. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWDU can decrease and the maximum of tWDU can increase by the capacitor tolerance. To allow for a valid watchdog window, choose a capacitor with tolerance such that tWDU(min) and tWDL(max) do not overlap. For the most accurate timing, use ceramic capacitors with COG dielectric material. As shown in Table 8-4, when using the minimum capacitor of 100 pF, the watchdog upper boundary is 62.74 ms; whereas with a 1-µF capacitor, the watchdog upper boundary is 77.455 seconds. If a CCWD capacitor is used, Equation 6 can be used to set tWDU the window watchdog upper boundary. The window watchdog lower boundary is dependent on the SET0 and SET1 pins because these pins set the window watchdog ratio of the lower boundary to upper boundary; Table 8-5 shows how tWDU can be used to calculate tWDL based on the SET0 and SET1 pins.

Table 8-4 tWDU Values for Common Ideal Capacitor Values
CCWD WATCHDOG UPPER BOUNDARY (tWDU) UNIT
MIN(1) TYP MAX(1)
100 pF 56.77 62.74 68.7 ms
1 nF 119.82 132.4 144.98 ms
10 nF 750 829 908 ms
100 nF 7054 7795 8536 ms
1 µF 70096 77455 84814 ms
(1) Minimum and maximum values are calculated using ideal capacitors.
Table 8-5 Programmable CWD Timing
INPUT WATCHDOG LOWER BOUNDARY (tWDL) WATCHDOG UPPER BOUNDARY (tWDU) UNIT
CWD SET0 SET1 MIN TYP MAX MIN(2) TYP(1) MAX(2)
CCWD 0 0 tWDU(min)x 0.125 tWDU x 0.125 tWDU(max) x 0.125 0.905 x tWDU(typ) tWDU(typ) 1.095 x tWDU(typ) s
0 1 tWDU(min) x 0.75 tWDU x 0.75 tWDU(max) x 0.75 0.905 x tWDU(typ) tWDU(typ) 1.095 x tWDU(typ) s
1 0 Watchdog disabled Watchdog disabled
1 1 tWDU(min) x 0.5 tWDU x 0.5 tWDU(max) x 0.5 0.905 x tWDU(typ) tWDU(typ) 1.095 x tWDU(typ) s
(1) Calculated from Equation 6 using ideal capacitors.
(2) The tWDU(min) and tWDU(max) include ICWD and VCWD minimum to maximum variation