TPS3852-Q1は高精度の電圧スーパバイザで、ウィンドウ・ウォッチドッグ・タイマが内蔵されています。TPS3852-Q1には高精度の低電圧スーパバイザが内蔵されており、低電圧スレッショルド(VITN)は-40℃~+125℃の規定の温度範囲全体にわたって0.8%の精度を実現しています。さらに、TPS3852-Q1には正確なヒステリシスが含まれているため、このデバイスは許容範囲の狭いシステムでの使用に理想的です。スーパバイザのRESET遅延は、高精度の遅延タイマにより15%精度を実現しています。
TPS3852-Q1にはプログラム可能なウィンドウ・ウォッチドッグ・タイマが内蔵されており、広範なアプリケーションに使用できます。専用ウォッチドッグ出力(WDO)により分解能が向上し、フォルト状況の性質を判定するために役立ちます。ウォッチドッグのタイムアウトは、外付けのコンデンサ、または工場でプログラムされるデフォルトの遅延設定によりプログラム可能です。ウォッチドッグはディセーブル可能で、開発プロセスにおいて望ましくないウォッチドッグのタイムアウトを回避できます。
TPS3852-Q1は、小型の3.00mm×3.00mm、8ピンのVSONパッケージで供給されます。TPS3852-Q1はウェッタブル・フランクを採用し、光学検査を容易に行えます。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
TPS3852-Q1 | VSON (8) | 3.00mm×3.00mm |
日付 | 改訂内容 | 注 |
---|---|---|
2017年2月 | * | 初版 |
NAME | NO. | I/O | DESCRIPTION |
---|---|---|---|
CWD | 2 | — | Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin and ground. Furthermore, this pin can also be connected by a 10-kΩ resistor to VDD, or leaving unconnected (NC) further enables the selection of the preset watchdog timeouts; see the Timing Requirements table. When using a capacitor, the TPS3852-Q1 determines the window watchdog upper boundary with Equation 1. See Table 4 and the CWD Functionality section for additional information. |
GND | 4 | — | Ground pin |
MR | 3 | I | Manual reset pin. A logical low on this pin issues a RESET. This pin is internally pulled up to VDD. RESET remains low for a fixed reset delay (tRST) time after MR is deasserted (high). |
RESET | 8 | O | Reset output. Connect RESET using a 1-kΩ to 100-kΩ resistor to the desired pullup voltage rail (VPU). RESET goes low when VDD goes below the undervoltage threshold (VITN). When VDD is within the normal operating range, the RESET timeout counter starts. At completion, RESET goes high. During startup, the state of RESET is undefined below the specified power-on-reset (POR) voltage (VPOR). Above POR, RESET goes low and remains low until the monitored voltage is within the correct operating range (above VITN + VHYST) and the RESET timeout is complete. |
SET1 | 5 | I | Logic input. Grounding the SET1 pin disables the watchdog timer. |
VDD | 1 | I | Supply voltage pin. For noisy systems, connecting a 0.1-μF bypass capacitor is recommended. |
WDI | 6 | I | Watchdog input. A falling transition (edge) must occur at this pin between the lower (tWDL(max)) and upper (tWDU(min)) window boundaries in order for WDO to not assert. When the watchdog is not in use, the SET1 pin can be used to disable the watchdog. The input at WDI is ignored when RESET or WDO are low (asserted) and also when the watchdog is disabled. If the watchdog is disabled, then WDI cannot be left unconnected and must be driven to either VDD or GND. |
WDO | 7 | O | Watchdog output. Connect WDO with a 1-kΩ to 100-kΩ resistor to the desired pullup voltage rail (VPU). WDO goes low (asserts) when a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout occurs, WDO goes low (asserts) for the set RESET timeout delay (tRST). When RESET goes low, WDO is in a high-impedance state. |
Thermal pad | — | Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage range | VDD | –0.3 | 7 | V |
Output voltage range | RESET, WDO | –0.3 | 7 | V |
Voltage ranges | SET1, WDI, MR | –0.3 | 7 | V |
CWD, CRST | –0.3 | VDD + 0.3(3) | ||
Output pin current | ±20 | mA | ||
Input current (all pins) | ±20 | mA | ||
Continuous total power dissipation | See Thermal Information | |||
Temperature | Operating junction, TJ(2) | –40 | 150 | °C |
Operating free-air, TA(2) | –40 | 150 | ||
Storage, Tstg | –65 | 150 |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V | |
Charged-device model (CDM), per AEC Q100-011 | ±750 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDD | Supply pin voltage | 1.6 | 6.5 | V | |
VSET1 | SET1 pin voltage | 0 | 6.5 | V | |
VMR | MR pin voltage | 0 | 6.5 | V | |
CCWD | Watchdog timing capacitor | 0.1(1) | 1000(1) | nF | |
CWD | Pullup resistor to VDD | 9 | 10 | 11 | kΩ |
RPU | Pullup resistor, RESET and WDO | 1 | 10 | 100 | kΩ |
IRESET | RESET pin current | 10 | mA | ||
IWDO | Watchdog output current | 10 | mA | ||
TJ | Junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS3852-Q1 | UNIT | |
---|---|---|---|
DRB (VSON) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 47.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 51.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 22.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 22.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 4.3 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
GENERAL CHARACTERISTICS | ||||||
VDD(3) | Supply voltage | 1.6 | 6.5 | V | ||
IDD | Supply current | 10 | 19 | µA | ||
RESET FUNCTION | ||||||
VPOR(2) | Power-on-reset voltage | IRESET = 15 µA, VOL(MAX) = 0.25 V | 0.8 | V | ||
VUVLO(1) | Undervoltage lockout voltage | 1.35 | V | |||
VITN | Undervoltage threshold accuracy, entering RESET |
VDD falling | VITN – 0.8% | VITN + 0.8% | ||
VHYST | Hysteresis voltage | VDD rising | 0.2% | 0.5% | 0.8% | |
IMR | MR pin internal pullup current | VMR = 0 V | 500 | 620 | 700 | nA |
WINDOW WATCHDOG FUNCTION | ||||||
ICWD | CWD pin charge current | CWD = 0.5 V | 337 | 375 | 413 | nA |
VCWD | CWD pin threshold voltage | 1.192 | 1.21 | 1.228 | V | |
VOL | RESET, WDO output low | VDD = 5 V, IRESET = IWDO = 3 mA |
0.4 | V | ||
ID | RESET, WDO output leakage current, open-drain |
VDD = VITN + VHYST, VRESET = VWDO = 6.5 V |
1 | µA | ||
VIL | Low-level input voltage (MR, SET1) | 0.25 | V | |||
VIH | High-level input voltage (MR, SET1) | 0.8 | V | |||
VIL(WDI) | Low-level input voltage (WDI) | 0.3 × VDD | V | |||
VIH(WDI) | High-level input voltage (WDI) | 0.8 × VDD | V |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
GENERAL | ||||||
tINIT | CWD pin evaluation period | 381 | µs | |||
Minimum MR, SET1 pin pulse duration | 1 | µs | ||||
Startup delay | 300 | µs | ||||
RESET FUNCTION | ||||||
tRST | Reset timeout period | 170 | 200 | 230 | ms | |
tRST-DEL | VDD to RESET delay | VDD = VITN + VHYST + 2.5% | 35 | µs | ||
VDD = VITN – 2.5% | 17 | |||||
tMR-DEL | MR to RESET delay | 200 | ns | |||
Watchdog Function | ||||||
tWDL | Window watchdog lower boundary | CWD = NC, SET1 = 0(1) | Watchdog disabled | |||
CWD = NC, SET1 = 1(1) | 680 | 800 | 920 | ms | ||
CWD = 10 kΩ to VDD, SET1 = 0(1) |
Watchdog disabled | |||||
CWD = 10 kΩ to VDD, SET1 = 1(1) |
1.48 | 1.85 | 2.22 | ms | ||
tWDU | Window watchdog upper boundary | CWD = NC, SET1 = 0(1) | Watchdog disabled | |||
CWD = NC, SET1 = 1(1) | 1360 | 1600 | 1840 | ms | ||
CWD = 10 kΩ to VDD, SET1 = 0(1) |
Watchdog disabled | |||||
CWD = 10 kΩ to VDD, SET1 = 1(1) |
9.35 | 11.0 | 12.65 | ms | ||
tWD-setup | Setup time required for device to respond to changes on WDI after being enabled | 150 | µs | |||
Minimum WDI pulse duration | 50 | ns | ||||
tWD-DEL | WDI to WDO delay | 50 | ns |
TPS3852G33-Q1 | ||
Includes G and H versions with 3.3-V nominal monitored voltage, total units = 15,536 |
VDD = 1.6 V |
TPS3852G33-Q1 entering undervoltage |
VITN = 3.168 V |
VDD = 1.6 V |
TPS3852G33-Q1 |
Includes G and H versions with 3.3-V nominal monitored voltage, total units = 15,536 |
Includes G and H versions with 3.3-V nominal monitored voltage, total units = 15,536 |
VDD = 6.5 V |
TPS3852G33-Q1 exiting undervoltage |
The TPS3852-Q1 is a high-accuracy voltage supervisor with an integrated window watchdog timer. This device includes a precision undervoltage supervisor with a threshold that achieves 0.8% accuracy over the specified temperature range of –40°C to +125°C. In addition, the TPS3852-Q1 includes accurate hysteresis on the threshold, making the device ideal for use with tight tolerance systems where voltage supervisors must ensure a RESET before the minimum supply tolerance of the microprocessor or system-on-a-chip (SoC) is reached.
NOTE:
R1 + R2 = 4.5 MΩ.Connect RESET to VPU through a 1-kΩ to 100-kΩ pullup resistor. RESET remains high (deasserted) when VDD is greater than the negative threshold voltage (VITN). If VDD falls below the negative threshold (VITN), then RESET is asserted, driving the RESET pin to low impedance. When VDD rises above VITN + VHYST, a delay circuit is enabled that holds RESET low for a specified reset delay period (tRST). When the reset delay has elapsed, the RESET pin goes to a high-impedance state and uses a pullup resistor to hold RESET high. The pullup resistor must be connected to the desired voltage rail to allow other devices to be connected at the correct interface voltage. To ensure proper voltage levels, give some consideration when choosing the pullup resistor values. The pullup resistor value is determined by output logic low voltage (VOL), leakage current (ID), and the current through the RESET pin IRESET.
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR causes RESET to assert. After MR returns to a logic high and VDD is above VITN + VHYST, RESET is deasserted after the reset delay time (tRST). If MR is not controlled externally, then MR can either be connected to VDD or left floating because the MR pin is internally pulled up. When MR is asserted, the watchdog is disabled and all signals input to WDI are ignored.
The TPS3852-Q1 features undervoltage detection for common rails between 1.8 V and 5 V. The voltage is monitored on the input rail of the device. If VDD drops below VITN, then RESET is asserted (driven low). When VDD is above VITN + VHYST, RESET deasserts after tRST, as shown in Figure 16. The internal comparator has built-in hysteresis that provides some noise immunity and ensures stable operation. Although not required in most cases, for noisy applications, good analog design practice is to place a 1-nF to 100-nF bypass capacitor close to the VDD pin to reduce sensitivity to transient voltages on the monitored signal.
This section provides information for the watchdog mode of operation.
The SET1 pin can enable and disable the watchdog timer. If SET1 is set to GND, the watchdog timer is disabled and WDI is ignored. When the watchdog is disabled, WDO is in a high-impedance state. If the watchdog timer is disabled, drive the WDI pin to either GND or VDD to ensure that there is no increase in IDD. When SET1 is logic high, the watchdog operates normally. The SET1 pin can be changed dynamically; however, if the watchdog is going from disabled to enabled there is a setup time tWD-setup where the watchdog does not respond to changes on WDI, as shown in Figure 17.
This section provides information for the window watchdog mode of operation. A window watchdog is typically employed in safety-critical applications where a traditional watchdog timer is inadequate. In a traditional watchdog there is a maximum time in which a pulse must be issued to prevent the reset from occurring. In a window watchdog, the pulse must be issued between a maximum lower window time (tWDL(max)) and the minimum upper window time (tWDU(min)) set by the CWD pin.
WDI is the watchdog timer input that controls the WDO output. The WDI input is triggered by the falling edge of the input signal. For the first pulse, the watchdog acts as a traditional watchdog timer; thus, the first pulse must be issued before tWDU(min). After the first pulse, to ensure proper functionality of the watchdog timer, always issue the WDI pulse within the window of tWDL(max) and tWDU(min). If the pulse is issued in this region, then WDO remains unasserted. Otherwise the device asserts WDO, putting the WDO pin into a low-impedance state.
The watchdog input (WDI) is a digital pin. In order to ensure there is no increase in IDD, drive the WDI pin to either VDD or GND at all times. Putting the pin to an intermediate voltage can cause an increase in supply current (IDD) because of the architecture of the digital logic gates. When RESET is asserted, the watchdog is disabled and all signals input to WDI are ignored. When RESET is no longer asserted, the device resumes normal operation and no longer ignores the signal on WDI. If the watchdog is disabled, drive the WDI pin to either VDD or GND.
The CWD pin provides the functionality of both high-precision, factory-programmed window watchdog timing options and user-programmable window watchdog timing. The CWD pin can be either pulled up to VDD through a resistor, have an external capacitor to ground, or be left floating. Every time that the device issues a reset event and the supply voltage is above VITN, the device tries to determine which of these three options is connected to the pin. There is an internal state machine that the device goes through to determine which option is connected to the CWD pin. The state machine can take up to 381 μs to determine if the CWD pin is left floating, pulled-up through a resistor, or connected to a capacitor.
If the CWD pin is being pulled up to VDD using a pullup resistor, then use a 10-kΩ resistor.
The TPS3852-Q1 features a window watchdog with an independent watchdog output (WDO). The independent watchdog output gives the flexibility to flag when there is a fault in the watchdog timing without performing an entire system reset. For legacy applications, WDO can be tied to RESET. When the RESET output is not asserted, the WDO signal maintains normal operation. However, when the RESET signal is asserted, the WDO pin goes to a high-impedance state. This is due to using the standard RESET timing options when a fault occurs on WDO. When RESET is unasserted, the window watchdog timer resumes normal operation.
Table 1 summarises the functional modes of the TPS3852-Q1.
VDD | WDI | WDO | RESET | ||
---|---|---|---|---|---|
VDD < VPOR | — | — | Undefined | ||
VPOR ≤ VDD < VDD(min) | Ignored | High | Low | ||
VDD(min) ≤ VDD ≤ VITN + VHYST(1) | Ignored | High | Low | ||
VDD > VITN(2) | tWDL(max) < tPULSE < tWDU(min)(3) | High | High | ||
tPULSE > tWDU(min)(3) | Low | High | |||
tPULSE < tWDL(max)(3) | Low | High |
When VDD is less than VPOR, RESET is undefined and can be either high or low. The state of RESET largely depends on the load that the RESET pin is experiencing.
When the voltage on VDD is less than VDD(min) and greater than or equal to VPOR, the RESET signal is asserted (logic low). When RESET is asserted, the watchdog output WDO is in a high-impedance state regardless of the WDI signal that is input to the device.
When VDD is greater than or equal to VDD(min), the RESET signal is determined by VDD. When RESET is asserted, WDO goes to a high-impedance state. WDO is then pulled high through the pullup resistor.