TPS3852-Q1 高精度電圧スーパバイザ、ウォッチドッグ・タイマ内蔵
- JAJSCZ7 February 2017 TPS3852-Q1
  
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TPS3852-Q1 高精度電圧スーパバイザ、ウォッチドッグ・タイマ内蔵

このリソースの元の言語は英語です。翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

1 特長

下記内容でAEC-Q100認定済み
- デバイス温度グレード1: 動作時周囲温度範囲　　　　–40°C～125°C
- デバイスHBM ESD分類レベル2
- デバイスCDM ESD分類レベルC4B
V_DD入力電圧範囲: 1.6V～6.5V
0.8%の電圧スレッショルド精度
低い消費電流: I_DD =10µA (標準値)
ウォッチドッグのタイムアウトをユーザーがプログラム可能
工場でプログラム済みの高精度のウォッチドッグとリセット・タイマ
- ±15%精度のWDTおよびRST遅延
オープン・ドレイン出力
マニュアル・リセット入力(MR)
高精度の電圧監視
- 1.8V～5.0Vの共通レールをサポート
- 4%および7%のスレッショルドを利用可能
- 0.5%のヒステリシス
ウォッチドッグのディセーブル機能
3mm×3mmの小型8ピンVSONパッケージで供給

2 アプリケーション

安全性が重要なアプリケーション
車載用視覚情報システム
車載用ADASシステム
テレマティクス制御ユニット
FPGAおよびASIC
マイクロコントローラおよびDSP

3 概要

TPS3852-Q1は高精度の電圧スーパバイザで、ウィンドウ・ウォッチドッグ・タイマが内蔵されています。TPS3852-Q1には高精度の低電圧スーパバイザが内蔵されており、低電圧スレッショルド(V_ITN)は-40℃～+125℃の規定の温度範囲全体にわたって0.8%の精度を実現しています。さらに、TPS3852-Q1には正確なヒステリシスが含まれているため、このデバイスは許容範囲の狭いシステムでの使用に理想的です。スーパバイザのRESET遅延は、高精度の遅延タイマにより15%精度を実現しています。

TPS3852-Q1にはプログラム可能なウィンドウ・ウォッチドッグ・タイマが内蔵されており、広範なアプリケーションに使用できます。専用ウォッチドッグ出力(WDO)により分解能が向上し、フォルト状況の性質を判定するために役立ちます。ウォッチドッグのタイムアウトは、外付けのコンデンサ、または工場でプログラムされるデフォルトの遅延設定によりプログラム可能です。ウォッチドッグはディセーブル可能で、開発プロセスにおいて望ましくないウォッチドッグのタイムアウトを回避できます。

TPS3852-Q1は、小型の3.00mm×3.00mm、8ピンのVSONパッケージで供給されます。TPS3852-Q1はウェッタブル・フランクを採用し、光学検査を容易に行えます。

製品情報⁽¹⁾

型番	パッケージ	本体サイズ（公称）
TPS3852-Q1	VSON (8)	3.00mm×3.00mm

提供されているすべてのパッケージについては、データシートの末尾にある注文情報を参照してください。

代表的なアプリケーション回路

低電圧スレッショルド(V_ITN)の精度と温度との関係

4 改訂履歴

日付	改訂内容	注
2017年2月	*	初版

5 Pin Configuration and Functions

DRB Package

8-Pin VSON

Top View

Pin Functions

NAME	NO.	I/O	DESCRIPTION
CWD	2	—	Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin and ground. Furthermore, this pin can also be connected by a 10-kΩ resistor to VDD, or leaving unconnected (NC) further enables the selection of the preset watchdog timeouts; see the Timing Requirements table. When using a capacitor, the TPS3852-Q1 determines the window watchdog upper boundary with Equation 1. See Table 4 and the CWD Functionality section for additional information.
GND	4	—	Ground pin
MR	3	I	Manual reset pin. A logical low on this pin issues a RESET. This pin is internally pulled up to V_DD. RESET remains low for a fixed reset delay (t_RST) time after MR is deasserted (high).
RESET	8	O	Reset output. Connect RESET using a 1-kΩ to 100-kΩ resistor to the desired pullup voltage rail (V_PU). RESET goes low when V_DD goes below the undervoltage threshold (V_ITN). When V_DD is within the normal operating range, the RESET timeout counter starts. At completion, RESET goes high. During startup, the state of RESET is undefined below the specified power-on-reset (POR) voltage (V_POR). Above POR, RESET goes low and remains low until the monitored voltage is within the correct operating range (above V_ITN + V_HYST) and the RESET timeout is complete.
SET1	5	I	Logic input. Grounding the SET1 pin disables the watchdog timer.
VDD	1	I	Supply voltage pin. For noisy systems, connecting a 0.1-μF bypass capacitor is recommended.
WDI	6	I	Watchdog input. A falling transition (edge) must occur at this pin between the lower (t_WDL(max)) and upper (t_WDU(min)) window boundaries in order for WDO to not assert. When the watchdog is not in use, the SET1 pin can be used to disable the watchdog. The input at WDI is ignored when RESET or WDO are low (asserted) and also when the watchdog is disabled. If the watchdog is disabled, then WDI cannot be left unconnected and must be driven to either VDD or GND.
WDO	7	O	Watchdog output. Connect WDO with a 1-kΩ to 100-kΩ resistor to the desired pullup voltage rail (V_PU). WDO goes low (asserts) when a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout occurs, WDO goes low (asserts) for the set RESET timeout delay (t_RST). When RESET goes low, WDO is in a high-impedance state.
Thermal pad		—	Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage range	VDD	–0.3	7	V
Output voltage range	RESET, WDO	–0.3	7	V
Voltage ranges	SET1, WDI, MR	–0.3	7	V
Voltage ranges	CWD, CRST	–0.3	V_DD + 0.3⁽³⁾	V
Output pin current			±20	mA
Input current (all pins)			±20	mA
Continuous total power dissipation		See Thermal Information
Temperature	Operating junction, T_J⁽²⁾	–40	150	°C
	Operating free-air, T_A⁽²⁾	–40	150
	Storage, T_stg	–65	150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Assume that T_J = T_A as a result of the low dissipated power in this device.

(3) The absolute maximum rating is V_DD + 0.3 V or 7.0 V, whichever is smaller.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾		±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011		±750	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_DD	Supply pin voltage	1.6		6.5	V
V_SET1	SET1 pin voltage	0		6.5	V
V_MR	MR pin voltage	0		6.5	V
C_CWD	Watchdog timing capacitor	0.1⁽¹⁾		1000⁽¹⁾	nF
CWD	Pullup resistor to VDD	9	10	11	kΩ
R_PU	Pullup resistor, RESET and WDO	1	10	100	kΩ
I_RESET	RESET pin current			10	mA
I_WDO	Watchdog output current			10	mA
T_J	Junction temperature	–40		125	°C

(1) Using a C_CWD capacitor of 0.1 nF or 1000 nF gives a t_WDU(typ) of 62.74 ms or 77.45 seconds, respectively.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS3852-Q1	UNIT
		DRB (VSON)
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	47.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	51.5	°C/W
R_θJB	Junction-to-board thermal resistance	22.2	°C/W
ψ_JT	Junction-to-top characterization parameter	1.3	°C/W
ψ_JB	Junction-to-board characterization parameter	22.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	4.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at V_ITN + V_HYST ≤ V_DD ≤ 6.5 V over the operating temperature range of –40°C ≤ T_A, T_J ≤ +125°C (unless otherwise noted); the open-drain pullup resistors are 10 kΩ for each output; typical values are at T_J = 25°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
GENERAL CHARACTERISTICS
V_DD⁽³⁾	Supply voltage		1.6		6.5	V
I_DD	Supply current			10	19	µA
RESET FUNCTION
V_POR⁽²⁾	Power-on-reset voltage	I_RESET = 15 µA, V_OL(MAX) = 0.25 V			0.8	V
V_UVLO⁽¹⁾	Undervoltage lockout voltage			1.35		V
V_ITN	Undervoltage threshold accuracy, entering RESET	V_DD falling	V_ITN – 0.8%		V_ITN + 0.8%
V_HYST	Hysteresis voltage	V_DD rising	0.2%	0.5%	0.8%
I_MR	MR pin internal pullup current	V_MR = 0 V	500	620	700	nA
WINDOW WATCHDOG FUNCTION
I_CWD	CWD pin charge current	CWD = 0.5 V	337	375	413	nA
V_CWD	CWD pin threshold voltage		1.192	1.21	1.228	V
V_OL	RESET, WDO output low	VDD = 5 V, I_RESET = I_WDO = 3 mA			0.4	V
I_D	RESET, WDO output leakage current, open-drain	VDD = V_ITN + V_HYST, V_RESET = V_WDO = 6.5 V			1	µA
V_IL	Low-level input voltage (MR, SET1)				0.25	V
V_IH	High-level input voltage (MR, SET1)		0.8			V
V_IL(WDI)	Low-level input voltage (WDI)				0.3 × V_DD	V
V_IH(WDI)	High-level input voltage (WDI)		0.8 × V_DD			V

(1) When V_DD falls below UVLO, RESET is driven low.

(2) When V_DD falls below V_POR, RESET and WDO are undefined.

(3) During power on, V_DD must be a minimum of 1.6 V for at least 300 µs before RESET correlates with V_DD.

6.6 Timing Requirements

			MIN	TYP	MAX	UNIT
GENERAL
t_INIT	CWD pin evaluation period			381		µs
	Minimum MR, SET1 pin pulse duration			1		µs
	Startup delay			300		µs
RESET FUNCTION
t_RST	Reset timeout period		170	200	230	ms
t_RST-DEL	V_DD to RESET delay	V_DD = V_ITN + V_HYST + 2.5%		35		µs
t_RST-DEL	V_DD to RESET delay	V_DD = V_ITN – 2.5%		17		µs
t_MR-DEL	MR to RESET delay			200		ns
Watchdog Function
t_WDL	Window watchdog lower boundary	CWD = NC, SET1 = 0⁽¹⁾	Watchdog disabled
		CWD = NC, SET1 = 1⁽¹⁾	680	800	920	ms
		CWD = 10 kΩ to VDD, SET1 = 0⁽¹⁾	Watchdog disabled
		CWD = 10 kΩ to VDD, SET1 = 1⁽¹⁾	1.48	1.85	2.22	ms
t_WDU	Window watchdog upper boundary	CWD = NC, SET1 = 0⁽¹⁾	Watchdog disabled
		CWD = NC, SET1 = 1⁽¹⁾	1360	1600	1840	ms
		CWD = 10 kΩ to VDD, SET1 = 0⁽¹⁾	Watchdog disabled
		CWD = 10 kΩ to VDD, SET1 = 1⁽¹⁾	9.35	11.0	12.65	ms
t_WD-setup	Setup time required for device to respond to changes on WDI after being enabled			150		µs
	Minimum WDI pulse duration			50		ns
t_WD-DEL	WDI to WDO delay			50		ns

(1) SET1 = 0 means V_SET1 < V_IL, SET1 = 1 means V_SET1 > V_IH.

1. See Figure 2 for WDI timing requirements.

Figure 1. Timing Diagram

Figure 2. TPS3852-Q1 Window Watchdog Timing

6.7 Typical Characteristics

all curves are taken at 25°C with 1.6 V ≤ VDD ≤ 6.5 V (unless otherwise noted)

Figure 3. Supply Current vs V_DD

TPS3852-Q1 tc_CWD_Current_Vs_temp_SBVS301-01.gif

Figure 5. CWD Charging Current vs Temperature

TPS3852G33-Q1

Figure 7. V_ITN Accuracy vs Temperature

Includes G and H versions with 3.3-V nominal monitored voltage,
total units = 15,536

Figure 9. V_ITN Accuracy Histogram

TPS3852-Q1 Vol_vs_Irst_1_6V_SBVS301-08.gif

VDD = 1.6 V

Figure 11. Low-Level RESET Voltage vs RESET Current

TPS3852-Q1 tc_propdelay_vs_overdrive_3.3V_enter_uv.gif

TPS3852G33-Q1 entering undervoltage

Figure 13. Propagation Delay vs Overdrive

V_ITN = 3.168 V

Figure 15. High-to-Low Glitch Immunity vs Temperature

VDD = 1.6 V

Figure 4. MR Threshold vs Temperature

TPS3852-Q1 tc_vitn_vhyst_acc_vs_temp_3_3.gif

TPS3852G33-Q1

Figure 6. V_ITN + V_HYST Accuracy vs Temperature

Includes G and H versions with 3.3-V nominal monitored voltage,
total units = 15,536

Figure 8. V_ITN + V_HYST Accuracy Histogram

Includes G and H versions with 3.3-V nominal monitored voltage,
total units = 15,536

Figure 10. Hysteresis Histogram

TPS3852-Q1 Vol_vs_Irst_6_5V_SBVS301-02.gif

VDD = 6.5 V

Figure 12. Low-Level RESET Voltage vs RESET Current

TPS3852-Q1 tc_propdelay_vs_overdrive_5V_exit_uv.gif

TPS3852G33-Q1 exiting undervoltage

Figure 14. Propagation Delay (t_RST) vs Overdrive

7 Detailed Description

7.1 Overview

The TPS3852-Q1 is a high-accuracy voltage supervisor with an integrated window watchdog timer. This device includes a precision undervoltage supervisor with a threshold that achieves 0.8% accuracy over the specified temperature range of –40°C to +125°C. In addition, the TPS3852-Q1 includes accurate hysteresis on the threshold, making the device ideal for use with tight tolerance systems where voltage supervisors must ensure a RESET before the minimum supply tolerance of the microprocessor or system-on-a-chip (SoC) is reached.

7.2 Functional Block Diagram

NOTE:

R₁ + R₂ = 4.5 MΩ.

7.3 Feature Description

7.3.1 RESET

Connect RESET to V_PU through a 1-kΩ to 100-kΩ pullup resistor. RESET remains high (deasserted) when V_DD is greater than the negative threshold voltage (V_ITN). If V_DD falls below the negative threshold (V_ITN), then RESET is asserted, driving the RESET pin to low impedance. When V_DD rises above V_ITN + V_HYST, a delay circuit is enabled that holds RESET low for a specified reset delay period (t_RST). When the reset delay has elapsed, the RESET pin goes to a high-impedance state and uses a pullup resistor to hold RESET high. The pullup resistor must be connected to the desired voltage rail to allow other devices to be connected at the correct interface voltage. To ensure proper voltage levels, give some consideration when choosing the pullup resistor values. The pullup resistor value is determined by output logic low voltage (V_OL), leakage current (I_D), and the current through the RESET pin I_RESET.

7.3.2 Manual Reset (MR)

The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR causes RESET to assert. After MR returns to a logic high and V_DD is above V_ITN + V_HYST, RESET is deasserted after the reset delay time (t_RST). If MR is not controlled externally, then MR can either be connected to V_DD or left floating because the MR pin is internally pulled up. When MR is asserted, the watchdog is disabled and all signals input to WDI are ignored.

7.3.3 Undervoltage Fault Detection

The TPS3852-Q1 features undervoltage detection for common rails between 1.8 V and 5 V. The voltage is monitored on the input rail of the device. If V_DD drops below V_ITN, then RESET is asserted (driven low). When V_DD is above V_ITN + V_HYST, RESET deasserts after t_RST, as shown in Figure 16. The internal comparator has built-in hysteresis that provides some noise immunity and ensures stable operation. Although not required in most cases, for noisy applications, good analog design practice is to place a 1-nF to 100-nF bypass capacitor close to the VDD pin to reduce sensitivity to transient voltages on the monitored signal.

Figure 16. Undervoltage Detection

7.3.4 Watchdog Mode

This section provides information for the watchdog mode of operation.

7.3.4.1 SET1

The SET1 pin can enable and disable the watchdog timer. If SET1 is set to GND, the watchdog timer is disabled and WDI is ignored. When the watchdog is disabled, WDO is in a high-impedance state. If the watchdog timer is disabled, drive the WDI pin to either GND or VDD to ensure that there is no increase in I_DD. When SET1 is logic high, the watchdog operates normally. The SET1 pin can be changed dynamically; however, if the watchdog is going from disabled to enabled there is a setup time t_WD-setup where the watchdog does not respond to changes on WDI, as shown in Figure 17.

TPS3852-Q1 ChangingSetPins_DisableToEnable_BVS.gif

Figure 17. Enabling and Disabling the Watchdog

7.3.4.2 Window Watchdog Timer

This section provides information for the window watchdog mode of operation. A window watchdog is typically employed in safety-critical applications where a traditional watchdog timer is inadequate. In a traditional watchdog there is a maximum time in which a pulse must be issued to prevent the reset from occurring. In a window watchdog, the pulse must be issued between a maximum lower window time (t_WDL(max)) and the minimum upper window time (t_WDU(min)) set by the CWD pin.

7.3.4.3 Watchdog Input (WDI)

WDI is the watchdog timer input that controls the WDO output. The WDI input is triggered by the falling edge of the input signal. For the first pulse, the watchdog acts as a traditional watchdog timer; thus, the first pulse must be issued before t_WDU(min). After the first pulse, to ensure proper functionality of the watchdog timer, always issue the WDI pulse within the window of t_WDL(max) and t_WDU(min). If the pulse is issued in this region, then WDO remains unasserted. Otherwise the device asserts WDO, putting the WDO pin into a low-impedance state.

The watchdog input (WDI) is a digital pin. In order to ensure there is no increase in I_DD, drive the WDI pin to either VDD or GND at all times. Putting the pin to an intermediate voltage can cause an increase in supply current (I_DD) because of the architecture of the digital logic gates. When RESET is asserted, the watchdog is disabled and all signals input to WDI are ignored. When RESET is no longer asserted, the device resumes normal operation and no longer ignores the signal on WDI. If the watchdog is disabled, drive the WDI pin to either VDD or GND.

7.3.4.4 CWD

The CWD pin provides the functionality of both high-precision, factory-programmed window watchdog timing options and user-programmable window watchdog timing. The CWD pin can be either pulled up to V_DD through a resistor, have an external capacitor to ground, or be left floating. Every time that the device issues a reset event and the supply voltage is above V_ITN, the device tries to determine which of these three options is connected to the pin. There is an internal state machine that the device goes through to determine which option is connected to the CWD pin. The state machine can take up to 381 μs to determine if the CWD pin is left floating, pulled-up through a resistor, or connected to a capacitor.

If the CWD pin is being pulled up to V_DD using a pullup resistor, then use a 10-kΩ resistor.

7.3.4.5 Watchdog Output (WDO)

The TPS3852-Q1 features a window watchdog with an independent watchdog output (WDO). The independent watchdog output gives the flexibility to flag when there is a fault in the watchdog timing without performing an entire system reset. For legacy applications, WDO can be tied to RESET. When the RESET output is not asserted, the WDO signal maintains normal operation. However, when the RESET signal is asserted, the WDO pin goes to a high-impedance state. This is due to using the standard RESET timing options when a fault occurs on WDO. When RESET is unasserted, the window watchdog timer resumes normal operation.

7.4 Device Functional Modes

Table 1 summarises the functional modes of the TPS3852-Q1.

Table 1. Device Functional Modes

V_DD	WDI	WDO	RESET
V_DD < V_POR	—	—	Undefined
V_POR ≤ V_DD < V_DD(min)	Ignored	High	Low
V_DD(min) ≤ V_DD ≤ V_ITN + V_HYST⁽¹⁾	Ignored	High	Low
V_DD > V_ITN⁽²⁾	t_WDL(max) < t_PULSE < t_WDU(min)⁽³⁾	High	High
	t_PULSE > t_WDU(min)⁽³⁾	Low	High
	t_PULSE < t_WDL(max)⁽³⁾	Low	High

(1) Only valid before V_DD goes above V_ITN + V_HYST.

(2) Only valid after V_DD goes above V_ITN + V_HYST.

(3) Where t_PULSE is the time between the falling edges on WDI.

7.4.1 V_DD is Below V_POR (V_DD < V_POR)

When V_DD is less than V_POR, RESET is undefined and can be either high or low. The state of RESET largely depends on the load that the RESET pin is experiencing.

7.4.2 Above Power-On-Reset, But Less Than V_DD(min) (V_POR ≤ V_DD < V_DD(min))

When the voltage on V_DD is less than V_DD(min) and greater than or equal to V_POR, the RESET signal is asserted (logic low). When RESET is asserted, the watchdog output WDO is in a high-impedance state regardless of the WDI signal that is input to the device.

7.4.3 Normal Operation (V_DD ≥ V_DD(min))

When V_DD is greater than or equal to V_DD(min), the RESET signal is determined by V_DD. When RESET is asserted, WDO goes to a high-impedance state. WDO is then pulled high through the pullup resistor.