SBVS149B September   2010  – January 2016 TPS386000-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parametric Measurement information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Monitoring
      2. 8.3.2 RESET Output
      3. 8.3.3 Manual Reset
      4. 8.3.4 Watchdog Timer
      5. 8.3.5 Immunity to SENSEn Voltage Transients
    4. 8.4 Device Functional Modes
      1. 8.4.1 Overview
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SENSE Input
      2. 9.1.2 Window Comparator
      3. 9.1.3 Sensing Voltage Less Than 0.4 V
      4. 9.1.4 Reset Delay Time
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

Follow these guidelines to lay out the printed-circuit-board (PCB) that is used for the TPS386000-Q1 family of devices.

  • Keep the traces to the timer capacitors as short as possible to optimize accuracy.
  • Avoid long traces from the SENSE pin to the resistor divider. Instead, run the long traces from the RSnH to VMON(n).
  • Place the VDD decoupling capacitor (CVDD) close to the device.
  • Avoid using long traces for the VDD supply node. The VDD capacitor (CVDD), along with parasitic inductance from the supply to the capacitor, can form an LC tank and create ringing with peak voltages above the maximum VDD voltage.

11.2 Layout Example

TPS386000-Q1 pcb_rgp_layout_bvs105.gif Figure 35. Example Layout (RGP Package)