8.3.1 Voltage Monitoring

Each SENSEn (n = 2, 3, 4) pin can be set to monitor any voltage threshold greater than 0.4 V using an external resistor divider. The SENSE1 pin is designed to monitor a 3.3-V supply with a 2.9-V threshold. A broad range of voltage thresholds can be supported, allowing these devices to be used in a wide array of applications.

The TPS386596 is relatively immune to short negative transients on the SENSEn pin. Sensitivity to transients depends on threshold overdrive, as shown in the typical performance graph TPS386596 SENSEn Minimum Pulse Width vs SENSEn Threshold Overdrive Voltage (Figure 4).

8.3.2 Manual Reset

The manual reset MR input allows external logic signal from processors, other logic circuits, and/or discrete sensors to initiate a reset. The typical application of a TPS386596 has its RESET output connected to processor. A logic low at MR causes RESET to assert. After MR returns to a logic high and SENSEn are above the respective voltage thresholds, RESET is released after a fixed 50-ms reset delay time. An internal 100-kΩ pullup to VDD is integrated on the MR input. There is also an internal 50-ns (typical) deglitch circuit.

8.3.3 Reset Output

In a typical application of the TPS386596, the RESET output is connected to the reset input of a processor (DSP, MCU, CPU, FPGA, ASIC, and so forth) or connected to the enable input of voltage regulators (DC-DC, LDO, and so forth).

The TPS386596 provides an open-drain reset output. Pullup resistors must be used to hold this line high when RESET is not asserted. By connecting a pullup resistor to the proper voltage rail (up to 6.5 V), the RESET output can be connected to other devices at the proper interface voltage level. The pullup resistor should be no smaller than 10 kΩ due to the finite impedance of the output transistor.

The RESET output is defined for V_DD > 0.9 V. To ensure that the target processor is properly reset, the V_DD supply input should be fed by the power rail and be available as early as possible in the application.

Table 1 shows a truth table of how the RESET output is asserted or released. Figure 1 provides a timing diagram that shows how RESET is asserted and deasserted in relation to MR and the SENSEn inputs. Once the conditions are met, the transitions from the asserted state to the release state are performed after a fixed 50-ms delay time.

Table 1. RESET Truth Table