JAJSLW0A October   2022  – November 2022 TPS38700

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device State Diagram
      2. 8.3.2 Built-In Self Test and Configuration Load
      3. 8.3.3 CLK32K
      4. 8.3.4 BACKUP State
      5. 8.3.5 FAILSAFE State
      6. 8.3.6 Transitioning Sequences
        1. 8.3.6.1 Sequence 1: Power Up
        2. 8.3.6.2 Sequence 2: Emergency Power Down
        3. 8.3.6.3 Sequence 3: Sleep Entry
        4. 8.3.6.4 Sequence 4: Sleep Exit
        5. 8.3.6.5 Sequence 5 & 6: Power Down from Active and Sleep States
        6. 8.3.6.6 Sequence 7: Sleep Exit Due to NRST_IN
        7. 8.3.6.7 Sequence 8: RESET Due to NRST_IN
        8. 8.3.6.8 Sequence 9: Failsafe Power Down
        9. 8.3.6.9 Output Sequencing
      7. 8.3.7 I2C
    4. 8.4 Register Map Table
      1. 8.4.1 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Guidelines
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2 Design Requirements

  • Eight different voltage rails supplied by DC/DC converters need to be properly sequenced in this design. The sequence order and timing requirements are outlined in Table 9-1 and Table 9-2.
  • Emergency power down functionality is optional.
  • Backup battery power supply required. This must be stepped down to a maximum value of 5.5 V in order to comply with the absolute maximum ratings of the VBBAT pin.
  • All detected failures in sequencing should be reported via an external hardware interrupt signal.
  • All detected failures should be logged in internal registers and be accessible to an external processor via I2C.

Table 9-1 Power Up and Power Down Sequence Requirement
ENABLE CHANNEL POWER UP SEQUENCE POSITION POWER DOWN SEQUENCE POSITION TIME BETWEEN POWER UP SIGNALS (μs) TIME BETWEEN POWER DOWN SIGNALS (μs)
EN1 1 4 625 625
EN2 1 1 625 625
EN3 2 3 625 625
EN4 2 3 625 625
EN5 3 2 625 625
EN6 4 1 625 625
EN7 1 1 625 625
EN8 2 3 625 625
Table 9-2 Sleep Entry and Sleep Exit Sequence Requirement
ENABLE CHANNEL SLEEP EXIT SEQUENCE POSITION SLEEP ENTRY SEQUENCE POSITION TIME BETWEEN SLEEP EXIT SIGNALS (μs) TIME BETWEEN SLEEP ENTRY SIGNALS (μs)
EN1 0 0 625 625
EN2 1 3 625 625
EN3 3 2 625 625
EN4 0 0 625 625
EN5 0 0 625 625
EN6 2 1 625 625
EN7 1 3 625 625
EN8 3 2 625 625