JAJSLW0A October   2022  – November 2022 TPS38700

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device State Diagram
      2. 8.3.2 Built-In Self Test and Configuration Load
      3. 8.3.3 CLK32K
      4. 8.3.4 BACKUP State
      5. 8.3.5 FAILSAFE State
      6. 8.3.6 Transitioning Sequences
        1. 8.3.6.1 Sequence 1: Power Up
        2. 8.3.6.2 Sequence 2: Emergency Power Down
        3. 8.3.6.3 Sequence 3: Sleep Entry
        4. 8.3.6.4 Sequence 4: Sleep Exit
        5. 8.3.6.5 Sequence 5 & 6: Power Down from Active and Sleep States
        6. 8.3.6.6 Sequence 7: Sleep Exit Due to NRST_IN
        7. 8.3.6.7 Sequence 8: RESET Due to NRST_IN
        8. 8.3.6.8 Sequence 9: Failsafe Power Down
        9. 8.3.6.9 Output Sequencing
      7. 8.3.7 I2C
    4. 8.4 Register Map Table
      1. 8.4.1 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Guidelines
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

At 2.2 V ≤  VDD ≤ 5.5 V, NRST/NIRQ Voltage = 10 kΩ to VDD, NRST/NIRQ load = 10 pF, and over the operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C, typical conditions at       VDD= 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Common Parameters
VDD Input supply voltage  2.2 5.5 V
VBBAT Backup battery voltage range 1.85 5.5 V
UVLO_VDDR UVLO VDD Rising threshold 2.2 V
UVLO_VDDF UVLO VDD Falling threshold/switch over to VBBAT 1.90 2 V
UVLO_VBBAT UVLO Battery backup Falling threshold 1.85 V
POR Power ON reset voltage, all outputs guaranteed to be stable above this value Falling threshold 1.39 V
IDD Supply current into VDD pin
ACT=High, SLEEP=High,  RTC=active
 		 VDD ≤ 5.5 V, power up sequence complete 45 75 µA
IDD Supply current into VDD pin
ACT=Low, SLEEP=Low,  RTC=active		 VDD ≤ 5.5 V ,power down sequence complete
 		 35 60 µA
IBBAT Supply current from VBBAT VBBAT ≤ 5.5 V 35 60 µA
ILKG_NRST Output leakage current (NRST) VDD=VNRST = 5.5 V 300 nA
ILKG_NIRQ Output leakage current (NIRQ) VDD=VNIRQ = 5.5 V 300 nA
ACT_L Logic Low input  0.36 V
ACT_H Logic high input  0.84 VDD - 0.2 V
SLEEP_L Logic Low input 0.36 V
SLEEP_H Logic high input 0.84 VDD - 0.2 V
SYNC_H Input High Io = 1mA 1.1 V
SYNC_L Input Low Io = 1mA 0.36 V
SYNC Internal Pull-up 100 kΩ
ACT Internal Pull down 100 kΩ
SLEEP Internal Pull down 100 kΩ
ENx Output High Push-Pull configuration, Io=1mA VDD-0.2 V
Output Low Push-Pull or Open-Drain (10 kΩ pull up) 0.1 V
R_ENx Enable Output resistance Push-Pull config 200 Ω
NRST Output Low Open-Drain (10 kΩ pull up) 0.1 V
NIRQ Output Low Open-Drain (10 kΩ pull up) 0.1 V
CLK32K Leakage test Open-Drain,4.7 kΩ pull up to 1.8V, 10pF capacitive load 100 nA
Output Low Open-Drain, Io = -1mA, pull up to 1.8V, 10pF                capacitive load 0.1 V
Acc_CLK32K Accuracy Early Boot t < 50ms, VDD > VDDmin -10 10 %
Accuracy Operating t > 1s, VDD > VDDmin -100 100 ppm
XTAL Fault Crystal Frequency fault detection -10 10 %
OSC Internal oscillator tolerance -5 5 %
Ilkg(BBAT) Leakge current from VBBAT VBBAT > 1.85V 300 nA
TSD Thermal Shutdown 165 ℃
TSD Hysterisis Thermal Shutdown Hysteresis 25 ℃
VIH_ALT NEM_PD,  NRST_IN,  NPWR_BTN Pin 10,11,12 Active Low, Open-Drain 1.1 V
VIL_ALT NEM_PD,  NRST_IN,  NPWR_BTN Pin 10,11,12 Active Low, Open-Drain 0.36 V
I2C Electrical Specifications
CB Capacitive load for SDA and SCL 400 pF
SDA, SCL Low Threshold, OTP = 1.2 V 0.36 V
SDA, SCL High Threshold, OTP = 1.2 V 0.84 V
SDA, SCL Low Threshold, OTP = 1.8 V 0.54 V
SDA, SCL High Threshold, OTP = 1.8 V 1.26 V
SDA, SCL Low Threshold, OTP = 3.3 V 0.84 V
SDA, SCL Low Threshold, OTP = 3.3 V 2.31 V
SDA, SCL Low Threshold, OTP = 5V 1.5 V
SDA, SCL High Threshold, OTP = 5V 3.5 V
SDA Output Low with 3 mA sink current 0.2 V