JAJSCZ8B March 2017 – February 2018 TPS3890-Q1
PRODUCTION DATA.
Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor near the VDD pin. If a capacitor is not connected to the CT pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected.