JAJSCT5A March   2016  – May 2016 TPS3890

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 User-Configurable RESET Delay Time
      2. 8.3.2 Manual Reset (MR) Input
      3. 8.3.3 RESET Output
      4. 8.3.4 SENSE Input
        1. 8.3.4.1 Immunity to SENSE Pin Voltage Transients
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 8.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage VDD –0.3 7 V
SENSE –0.3 7
RESET –0.3 7
MR –0.3 7
VCT –0.3 7
Current RESET –20 20 mA
Temperature Operating junction temperature, TJ –40 125 °C
Storage temperature, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Power-supply voltage 1.5 5.5 V
VSENSE SENSE voltage 0 5.5 V
VRESET RESET pin voltage 0 5.5 V
IRESET RESET pin current –5 5 mA
CIN Input capacitor, VDD pin 0 0.1 µF
CCT Reset timeout capacitor, CT pin 0 22 µF
RPU Pullup resistor, RESET pin 1 1000 kΩ
TJ Junction temperature (free-air temperature) –40 25 125 ℃

7.4 Thermal Information

THERMAL METRIC(1) TPS3890 UNIT
DSE (WSON)
6 PINS
RθJA Junction-to-ambient thermal resistance 321.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 207.9 °C/W
RθJB Junction-to-board thermal resistance 281.5 °C/W
ψJT Junction-to-top characterization parameter 42.4 °C/W
ψJB Junction-to-board characterization parameter 284.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 142.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, and MR = VDD (unless otherwise noted); typical values are at VDD = 5.5 V and TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Input supply voltage 1.5 5.5 V
VPOR Power-on reset voltage VOL(max) = 0.2 V, IRESET = 15 µA 0.8 V
IDD Supply current (into VDD pin) VDD = 3.3 V, IRESET = 0 mA,
–40°C < TJ < 85°C		 2.09 3.72 µA
VDD = 3.3 V, IRESET = 0 mA,
–40°C < TJ < 105°C		 4.5
VDD= 3.3 V, IRESET = 0 mA 5.8
VDD = 5.5 V, IRESET = 0 mA,
–40°C < TJ < 85°C		 2.29 4
VDD = 5.5 V, IRESET = 0 mA,
–40°C < TJ < 105°C		 5.2
VDD = 5.5 V, IRESET = 0 mA 6.5
VITN, VITP SENSE input threshold voltage accuracy –1% ±0.5% 1%
VHYST Hysteresis(1) 0.325% 0.575% 0.825%
ISENSE Input current VSENSE = 5 V 8 µA
VSENSE = 5 V, TPS389001, TPS389012 10 100 nA
ICT CT pin charge current 0.90 1.15 1.35 µA
VCT CT pin comparator threshold voltage 1.17 1.23 1.29 V
RCT CT pin pulldown resistance When RESET is deasserted 200 Ω
VIL Low-level input voltage (MR pin) 0.25 × VDD V
VIH High-level output voltage 0.7 x VDD V
VOL Low-level output voltage VDD ≥ 1.5 V, IRESET = 0.4 mA 0.25 V
VDD ≥ 2.7 V, IRESET = 2 mA 0.25
VDD ≥ 4.5 V, IRESET = 3 mA 0.3
ILKG(OD) Open-drain output leakage High impedance,
VSENSE = VRESET = 5.5 V		 250 nA
(1) VHYST = [(VITP – VITN) / VITN] × 100%.

7.6 Timing Requirements

over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, MR = VDD, and 5% input overdrive(1) (unless otherwise noted); typical values are at VDD = 5.5 V and TJ = 25°C
MIN NOM MAX UNIT
tPD(f) SENSE (falling) to RESET propagation delay CT = open, VDD = 3.3 V 18 µs
CT = open, VDD = 5.5 V 8
tPD(r) SENSE (rising) to RESET propagation delay CT = open, VDD = 3.3 V 25 µs
tGI(SENSE) SENSE pin glitch immunity VDD = 5.5 V 9 µs
tGI(MR) MR pin glitch immunity VDD = 5.5 V 100 ns
tMRW MR pin pulse duration to assert RESET 1 µs
td(MR) MR pin low to out delay 250 ns
tSTRT Startup delay 325 µs
(1) Overdrive = | (VIN / VTHRESH – 1) × 100% |.
TPS3890 td_tps3803_bvs050.gif Figure 1. Timing Diagram

7.7 Typical Characteristics

over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, and MR = VDD (unless otherwise noted)
TPS3890 D001-SLVSD65-01_Vit-.gif
Figure 2. VITN Accuracy vs Temperature
TPS3890 D019_SLVSD65_Vitp_Histogrom.gif
Tested at VDD = 1.5 V and VDD = 5.5 V, total tests = 136,348
Figure 4. VITN Accuracy Histogram
TPS3890 D021_SLVSD65_Hyst_Histogrom.gif
i.
Tested at VDD = 1.5 V and VDD = 5.5 V, total tests = 136,348
Figure 6. Hysteresis Histogram
TPS3890 D003-SLVSD65-01_Iq_MR_6p5V.gif
MR = VDD
Figure 8. Supply Current vs Power-Supply Voltage
TPS3890 D006-SLVSD65-03_MR_Thresh_VCC_1p5V.gif
VDD = 1.5 V
Figure 10. MR Threshold vs Temperature
TPS3890 D008-SLVSD65-01_Startup_Delay.gif
Figure 12. Startup Delay vs Temperature
TPS3890 D010-SLVSD65-01_Prop_Delay_LH_1p5V.gif
VDD = 1.5 V
Figure 14. Propagation Delay (tPD(r)) vs Overdrive
TPS3890 D012-SLVSD65-01_Prop_Delay_HL_1p5V.gif
VDD = 1.5 V
Figure 16. Propagation Delay (tPD(f)) vs Overdrive
TPS3890 D014-SLVSD65-01_Glitch_Rejection_1p5V.gif
VDD = 1.5 V
Figure 18. Low-to-High Glitch Immunity vs Temperature
TPS3890 D018-SLVSD65-04.gif
VDD = 1.5 V
Figure 20. High-to-Low Glitch Immunity vs Temperature
TPS3890 D016-SLVSD65-01_Vol_1p5.gif
VDD = 1.5 V
Figure 22. Low-Level Output Voltage vs RESET Current
TPS3890 D002-SLVSD65-01_Vit_plus.gif
Figure 3. VITP Accuracy vs Temperature
TPS3890 D020_SLVSD65_Vitn_Histogrom.gif
Tested at VDD = 1.5 V and VDD = 5.5 V, total tests = 136,348
Figure 5. VITP Accuracy Histogram
TPS3890 D005-SLVSD65-01_CT_Current.gif
Figure 7. CT Current vs Temperature
TPS3890 D004-SLVSD65-02_Iq_MR_0V.gif
MR = 0 V
Figure 9. Supply Current vs Power-Supply Voltage
TPS3890 D007-SLVSD65-01_MR_Thresh_VCC_6p5V.gif
VDD = 5.5 V
Figure 11. MR Threshold vs Temperature
TPS3890 D009-SLVSD65-02_Prop_Delay_LH_6p5V.gif
VDD = 5.5 V
Figure 13. Propagation Delay (tPD(r)) vs Overdrive
TPS3890 D011-SLVSD65-02_Prop_Delay_HL_6p5V.gif
VDD = 5.5 V
Figure 15. Propagation Delay (tPD(f)) vs Overdrive
TPS3890 D013-SLVSD65-01_Glitch_Rejection_6p5V.gif
VDD = 5.5 V
Figure 17. Low-to-High Glitch Immunity vs Temperature
TPS3890 D017-SLVSD65-01.gif
VDD = 5.5 V
Figure 19. High-to-Low Glitch Immunity vs Temperature
TPS3890 D015-SLVSD65-02_Vol_5p5.gif
VDD = 5.5 V
Figure 21. Low-Level Output Voltage vs RESET Current