JAJSQG3 データシート

JAJSQG3B march 2022 – may 2023 TPS389006-Q1

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RTE|16
- MPQF149D

サーマルパッド・メカニカル・データ

RTE|16
- QFND630A

発注情報

8.5.1 BANK0 Registers

Table 8-4 lists the memory-mapped registers for the BANK0 registers. All register offset addresses not listed in Table 8-4 should be considered as reserved locations and the register contents should not be modified.

Table 8-4 BANK0 Registers

Address	Acronym	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x10	INT_SRC	F_OTHER	RSVD				TEST	CONTROL	MONITOR
0x11	INT_MONITOR	SEQ_ON	SEQ_OFF	SEQ_EXS	SEQ_ENS	OV_LF	OV_HF	UV_LF	UV_HF
0x12	INT_UVHF	RSVD		UVHF[N]
0x14	INT_UVLF	RSVD		UVLF[N]
0x16	INT_OVHF	RSVD		OVHF[N]
0x18	INT_OVLF	RSVD		OVLF[N]
0x1A	INT_SEQ_ON	RSVD		F_SEQ_ON[N]
0x1C	INT_SEQ_OFF	RSVD		F_SEQ_OFF[N]
0x1E	INT_SEQ_EXS	RSVD		F_SEQ_EXS[N]
0x20	INT_SEQ_ENS	RSVD		F_SEQ_ENS[N]
0x22	INT_CONTROL	RSVD			F_CRC	F_NIRQ	F_TSD	F_SYNC	F_PEC
0x23	INT_TEST	RSVD				ECC_SEC	ECC_DED	I_BIST_C	BIST
0x24	INT_VENDOR	LDO_OV_Error		Freq_DEV_Error		SHORT_DET	OPEN_DET	RSVD
0x30	VMON_STAT	FAILSAFE	ST_BIDT_C	ST_VDD	ST_NIRQ	ST_ACTSLP	ST_ACTSHDN	ST_SYNC	RSVD
0x31	TEST_INFO	RSVD		ECC_SEC	ECC_DED	BIST_VM	BIST_NVM	BIST_L	BIST_A
0x32	OFF_STAT	RSVD		VIN[N]
0x34	SEQ_REC_STAT	REC_ACTIVE	SEQ		TS_RDY	SEQ_ON_RDY	SEQ_OFF_RDY	SEQ_EXS_RDY	SEQ_ENS_RDY
0x35	SEQ_OW_STAT	RSVD			TS_OW	SEQ_ON_OW	SEQ_OFF_OW	SEQ_EXS_OW	SEQ_ENS_OW
0x36	SEQ_ORD_STAT	SYNC_COUNT[7:0]
0x40	MON_LVL[1]	ADC[7:0]
0x41	MON_LVL[2]	ADC[7:0]
0x42	MON_LVL[3]	ADC[7:0]
0x43	MON_LVL[4]	ADC[7:0]
0x44	MON_LVL[5]	ADC[7:0]
0x45	MON_LVL[6]	ADC[7:0]
0x50	SEQ_ON_LOG[1]	ORDER[7:0]
0x51	SEQ_ON_LOG[2]	ORDER[7:0]
0x52	SEQ_ON_LOG[3]	ORDER[7:0]
0x53	SEQ_ON_LOG[4]	ORDER[7:0]
0x54	SEQ_ON_LOG[5]	ORDER[7:0]
0x55	SEQ_ON_LOG[6]	ORDER[7:0]
0x60	SEQ_OFF_LOG[1]	ORDER[7:0]
0x61	SEQ_OFF_LOG[2]	ORDER[7:0]
0x62	SEQ_OFF_LOG[3]	ORDER[7:0]
0x63	SEQ_OFF_LOG[4]	ORDER[7:0]
0x64	SEQ_OFF_LOG[5]	ORDER[7:0]
0x65	SEQ_OFF_LOG[6]	ORDER[7:0]
0x70	SEQ_EXS_LOG[1]	ORDER[7:0]
0x71	SEQ_EXS_LOG[2]	ORDER[7:0]
0x72	SEQ_EXS_LOG[3]	ORDER[7:0]
0x73	SEQ_EXS_LOG[4]	ORDER[7:0]
0x74	SEQ_EXS_LOG[5]	ORDER[7:0]
0x75	SEQ_EXS_LOG[6]	ORDER[7:0]
0x80	SEQ_ENS_LOG[1]	ORDER[7:0]
0x81	SEQ_ENS_LOG[2]	ORDER[7:0]
0x82	SEQ_ENS_LOG[3]	ORDER[7:0]
0x83	SEQ_ENS_LOG[4]	ORDER[7:0]
0x84	SEQ_ENS_LOG[5]	ORDER[7:0]
0x85	SEQ_ENS_LOG[6]	ORDER[7:0]
0x90	SEQ_TIME_MSB[1]	CLOCK[7:0]
0x91	SEQ_TIME_LSB[1]	CLOCK[7:0]
0x92	SEQ_TIME_MSB[2]	CLOCK[7:0]
0x93	SEQ_TIME_LSB[2]	CLOCK[7:0]
0x94	SEQ_TIME_MSB[3]	CLOCK[7:0]
0x95	SEQ_TIME_LSB[3]	CLOCK[7:0]
0x96	SEQ_TIME_MSB[4]	CLOCK[7:0]
0x97	SEQ_TIME_LSB[4]	CLOCK[7:0]
0x98	SEQ_TIME_MSB[5]	CLOCK[7:0]
0x99	SEQ_TIME_LSB[5]	CLOCK[7:0]
0x9A	SEQ_TIME_MSB[6]	CLOCK[7:0]
0x9B	SEQ_TIME_LSB[6]	CLOCK[7:0]
0xF0	BANK_SEL	RSVD						BANK_SELECT	BANK
0xF1	PROT1	RSVD		WRKC	WRKS	CFG	IEN	MON	SEQ
0xF2	PROT2	RSVD		WRKC	WRKS	CFG	IEN	MON	SEQ
0xF3	PROT_MON2	RSVD		MON[N]
0xF9	I2CADDR	RSVD	ADDR_NVM[3:0]				ADDR_STRAP[2:0]
0xFA	DEV_CFG	RSVD							SOC_IF

Complex bit access types are encoded to fit into small table cells. Table 8-5 shows the codes that are used for access types in this section.

Table 8-5 BANK0 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
W1C	W 1C	Write 1 to clear
Reset or Default Value
-n		Value after reset or the default value

8.5.1.1 INT_SRC Register (Address = 0x10) [Default = X]

INT_SRC is shown in Table 8-6.

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Global Interrupt Source Status register. This register contains fault interrupts on UV/OV HF/LF interrupts and internal fault interrupt and other interrupt. INT_SRC represents the reason why NIRQ was asserted. When the host processor receives NIRQ, the processor can read this register to quickly determine the source of the interrupt. If this register is clear, then TPS389006-Q1 did not assert NIRQ.

Table 8-6 INT_SRC Register Field Descriptions

Bit	Field	Type	Default	Description
7	F_OTHER	R	X	Vendor specific internal fault. Details reported in INT_F_OTHER. This bit represents the ORed value of all bits in INT_F_OTHER. 0b = No fault reported in INT_F_OTHER 1b = Fault reported in INT_F_OTHER
6:3	RSVD	R	X	RSVD
2	TEST	R	X	Internal test or configuration load fault. Details reported in INT_TEST. Represents ORed value of all bits in INT_TEST. 0b = No test/configuration fault detected 1b = Test/configuration fault detected
1	CONTROL	R	X	Control status or communication fault. Details reported in INT_CONTROL. Represents ORed value of all bits in INT_CONTROL. 0b = No status or communication fault detected 1b = Status or communication fault detected
0	MONITOR	R	X	Voltage or sequence monitor fault. Details reported in INT_MONITOR. Represents ORed value of all bits in INT_MONITOR. 0b = No voltage or sequence fault detected 1b = Voltage or sequence fault detected

8.5.1.2 INT_MONITOR Register (Address = 0x11) [Default = X]

INT_MONITOR is shown in Table 8-7.

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Voltage and Sequence Monitor Interrupt Status register. This register contains fault interrupts for sequence entry/exit from act/sleep modes and HF and LF faults.

Table 8-7 INT_MONITOR Register Field Descriptions

Bit	Field	Type	Default	Description
7	SEQ_ON	R	X	Power ON Sequence Fault. Details reported in INT_SEQ_ON. Represents ORed value of all bits in INT_SEQ_ON. A Power ON Sequence fault occurs when the content of SEQ_ON_LOG[N] register does not match the value defined in SEQ_ON_EXP[N] register. 0b = No Power ON Sequence fault detected 1b = Power ON Sequence fault detected
6	SEQ_OFF	R	X	Power OFF Sequence Fault. Details reported in INT_SEQ_OFF. Represents ORed value of all bits in INT_SEQ_OFF. A Power OFF Sequence fault occurs when the content of SEQ_OFF_LOG[N] register does not match the value defined in SEQ_OFF_EXP[N] register. 0b = No Power OFF Sequence fault detected 1b = Power OFF Sequence fault detected
5	SEQ_EXS	R	X	Exit Sleep Sequence Fault. Details reported in INT_SEQ_EXS. Represents ORed value of all bits in INT_SEQ_EXS. An Exit Sleep Sequence fault occurs when the content of SEQ_EXS_LOG[N] register does not match the value defined in SEQ_EXS_EXP[N] register. 0b = No Exit Sleep Sequence fault detected 1b = Exit Sleep Sequence fault detected
4	SEQ_ENS	R	X	Entry Sleep Sequence Fault. Details reported in INT_SEQ_ENS. Represents ORed value of all bits in INT_SEQ_ENS. An Entry Sleep Sequence fault occurs when the content of SEQ_ENS_LOG[N] register does not match the value defined in SEQ_ENS_EXP[N] register. 0b = No Entry Sleep Sequence fault detected 1b = Entry Sleep Sequence fault detected
3	OV_LF	R	X	Over-Voltage Low Frequency Fault. Details reported in INT_OVLF. Represents ORed value of all bits in INT_OVLF. 0b = No OVLF fault detected 1b = OVLF fault detected
2	OV_HF	R	X	Over-Voltage High Frequency Fault. Details reported in INT_OVHF. Represents ORed value of all bits in INT_OVHF. 0b = No OVHF fault detected 1b = OVHF fault detected
1	UV_LF	R	X	Under-Voltage Low Frequency Fault. Details reported in INT_UVLF. Represents ORed value of all bits in INT_UVLF. 0b = No UVLF fault detected 1b = UVLF fault detected
0	UV_HF	R	X	Under-Voltage High Frequency Fault. Details reported in INT_UVHF. Represents ORed value of all bits in INT_UVHF. 0b = No UVHF fault detected 1b = UVHF fault detected

8.5.1.3 INT_UVHF Register (Address = 0x12) [Default = X]

INT_UVHF is shown in Table 8-8.

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High Frequency channel Under-Voltage Interrupt Status register. This register contains informtation on which channel had a UV HF fault.

Table 8-8 INT_UVHF Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W1C	X	RSVD
5:0	UVHF[N]	R/W1C	X	Under-Voltage High Frequency Fault for channel N (1 through 6). Trips if channel N High Frequency signal goes below UV_HF[N]. The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write- 1-to-clear. Write- 1-to-clear will clear the bit only if the UVHF fault condition is also removed (channel N High Frequency signal is above UV_HF[N]). 0b = Channel N has no UVHF fault detected (or interrupt disabled in IEN_UVHF register) 1b = Channel N has UVHF fault detected

8.5.1.4 INT_UVLF Register (Address = 0x14) [Default = X]

INT_UVLF is shown in Table 8-9.

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Low Frequency channel Under-Voltage Interrupt Status register. This register contains informtation on which channel had a UV LF fault.

Table 8-9 INT_UVLF Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W1C	X	RSVD
5:0	UVLF[N]	R/W1C	X	Under-Voltage Low Frequency Fault for channel N (1 through 6). Trips if channel N Low Frequency signal goes below UV_LF[N]. The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write- 1-to-clear. Write- 1-to-clear will clear the bit only if the UVLF fault condition is also removed (channel N Low Frequency signal is above UV_LF[N]). 0b = Channel N has no UVLF fault detected (or interrupt disabled in IEN_UVLF register) 1b = Channel N has UVLF fault detected

8.5.1.5 INT_OVHF Register (Address = 0x16) [Default = X]

INT_OVHF is shown in Table 8-10.

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High Frequency channel Over-Voltage Interrupt Status register. This register contains informtation on which channel had an OV HF fault.

Table 8-10 INT_OVHF Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W1C	X	RSVD
5:0	OVHF[N]	R/W1C	X	Over-Voltage High Frequency Fault for channel N (1 through 6). Trips if channel N High Frequency signal goes above OV_HF[N]. The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write- 1-to-clear. Write- 1-to-clear will clear the bit only if the OVHF fault condition is also removed (channel N High Frequency signal is below OV_HF[N]). 0b = Channel N has noOVHF fault detected (or interrupt disabled in IEN_OVHF register) 1b = Channel N has OVHF fault detected

8.5.1.6 INT_OVLF Register (Address = 0x18) [Default = X]

INT_OVLF is shown in Table 8-11.

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Low Frequency channel Over-Voltage Interrupt Status register. This register contains informtation on which channel had an OV LF fault.

Table 8-11 INT_OVLF Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W1C	X	RSVD
5:0	OVLF[N]	R/W1C	X	Over-Voltage Low Frequency Fault for channel N (1 through 6). Trips if channel N Low Frequency signal goes above OV_LF[N]. The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write- 1-to-clear. Write- 1-to-clear will clear the bit only if the OVLF fault condition is also removed (channel N Low Frequency signal is below OV_LF[N]). 0b = Channel N has no OVLF fault detected (or interrupt disabled in IEN_OVLF register) 1b = Channel N has OVLF fault detected

8.5.1.7 INT_SEQ_ON Register (Address = 0x1A) [Default = X]

INT_SEQ_ON is shown in Table 8-12.

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Power ON Sequence (ACT/ SLEEP 0 to 1) Interrupt Status register. This register contains informtation on which channel did not follow on sequence.

Table 8-12 INT_SEQ_ON Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W1C	X	RSVD
5:0	F_SEQ_ON[N]	R/W1C	X	Power ON Sequence Fault for channel N (1 through 6). Trips if channel N recorded Power ON Sequence counter in SEQ_ON_LOG[N] register does not match the value defined in SEQ_ON_EXP[N] register. The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write- 1-to-clear. Write- 1-to-clear will clear the bit. The bit will be set again during next sequence if the same fault is detected. 0b = Channel N has no Power ON Sequence fault detected (or interrupt disabled in IEN_SEQ_ON register) 1b = Channel N has Power ON Sequence fault detected

8.5.1.8 INT_SEQ_OFF Register (Address = 0x1C) [Default = X]

INT_SEQ_OFF is shown in Table 8-13.

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Power OFF Sequence (ACT/ SLEEP 1 to 0) Interrupt Status register. This register contains informtation on which channel did not follow off sequence.

Table 8-13 INT_SEQ_OFF Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W1C	X	RSVD
5:0	F_SEQ_OFF[N]	R/W1C	X	Power OFF Sequence Fault for channel N (1 through 6). Trips if channel N recorded Power OFF Sequence counter in SEQ_OFF_LOG[N] register does not match the value defined in SEQ_OFF_EXP[N] register. The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write- 1-to-clear. Write- 1-to-clear will clear the bit. The bit will be set again during next sequence if the same fault is detected. 0b = Channel N has no Power OFF Sequence fault detected (or interrupt disabled in IEN_SEQ_OFF register) 1b = Channel N has Power OFF Sequence fault detected

8.5.1.9 INT_SEQ_EXS Register (Address = 0x1E) [Default = X]

INT_SEQ_EXS is shown in Table 8-14.

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Exit Sleep Sequence (ACT/ SLEEP 0 to 1) Interrupt Status register. This register contains informtation on which channel did not follow sleep exit sequence.

Table 8-14 INT_SEQ_EXS Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W1C	X	RSVD
5:0	F_SEQ_EXS[N]	R/W1C	X	Exit Sleep Sequence Fault for channel N (1 through 6). Trips if channel N recorded Exit Sleep Sequence counter in SEQ_EXS_LOG[N] register does not match the value defined in SEQ_EXS_EXP[N] register. The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write- 1-to-clear. Write- 1-to-clear will clear the bit. The bit will be set again during next sequence if the same fault is detected. 0b = Channel N has no Exit Sleep Sequence fault detected (or interrupt disabled in IEN_SEQ_EXS register) 1b = Channel N has Exit Sleep Sequence fault detected

8.5.1.10 INT_SEQ_ENS Register (Address = 0x20) [Default = X]

INT_SEQ_ENS is shown in Table 8-15.

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Entry Sleep Sequence (SLEEP 1 to 0) Interrupt Status register. This register contains informtation on which channel did not follow sleep entry sequence.

Table 8-15 INT_SEQ_ENS Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W1C	X	RSVD
5:0	F_SEQ_ENS[N]	R/W1C	X	Entry Sleep Sequence Fault for channel N (1 through 6). Trips if channel N recorded Entry Sleep Sequence counter in SEQ_ENS_LOG[N] register does not match the value defined in SEQ_ENS_EXP[N] register. 0b = Channel N has no Entry Sleep Sequence fault detected (or interrupt disabled in IEN_SEQ_ENS register) 1b = Channel N has Entry Sleep Sequence fault detected

8.5.1.11 INT_CONTROL Register (Address = 0x22) [Default = X]

INT_CONTROL is shown in Table 8-16.

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Control and Communication Interrupt Status Register.

Table 8-16 INT_CONTROL Register Field Descriptions

Bit	Field	Type	Default	Description
7:5	RSVD	R/W1C	X	RSVD
4	F_CRC	R/W1C	X	Runtime register CRC Fault: The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write- 1-to-clear. Write- 1-to-clear will clear the bit. The bit will be set again during next register CRC check if the same fault is detected. 0b = No fault detected (or IEN_CONTROL.RT_CRC is disabled) 1b = Register CRC fault detected
3	F_NIRQ	R/W1C	X	Interrupt pin fault (fault bit always enabled no enable bit available): The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write- 1-to-clear. Write- 1-to-clear will clear the bit only if the NIRQ fault condition is also removed. 0b = No fault detected on NIRQ pin 1b = Low resistance path to supply detected on NIRQ pin
2	F_TSD	R/W1C	X	Thermal Shutdown fault: The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write- 1-to-clear. Write- 1-to-clear will clear the bit only if the TSD fault condition is also removed. 0b = No TSD fault detected (or IEN_CONTROL.TSD is disabled) 1b = TSD fault detected
1	F_SYNC	R/W1C	X	SYNC pin fault: The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write- 1-to-clear. Write- 1-to-clear will clear the bit only if the SYNC fault condition is also removed. 0b = No fault detected on SYNC pin (or IEN_CONTROL.SYNC is disabled) 1b = Low resistance path to supply detected on SYNC pin
0	F_PEC	R/W1C	X	Packet Error Checking fault: The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write- 1-to-clear. Write- 1-to-clear will clear the bit. The bit will be set again during next I2C transaction if the same fault is detected.

8.5.1.12 INT_TEST Register (Address = 0x23) [Default = X]

INT_TEST is shown in Table 8-17.

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Internal Test and Configuration Load Interrupt Status Register.

Table 8-17 INT_TEST Register Field Descriptions

Bit	Field	Type	Default	Description
7:4	RSVD	R/W1C	X	RSVD
3	ECC_SEC	R/W1C	X	ECC single-error corrected on OTP configuration load: Write- 1-to-clear will clear the bit. The bit will be set again during next OTP configuration load if the same fault is detected. 0b = No single-error corrected (or IEN_TEST.ECC_SEC is disabled) 1b = Single-error corrected
2	ECC_DED	R/W1C	X	ECC double-error detected on OTP configuration load: The fault bit is always enabled (there is no associated interrupt enable bit). Write- 1-to-clear will clear the bit. The bit will be set again during next OTP configuration load if the same fault is detected. 0b = No double-error detected on OTP load 1b = Double-error detected on OTP load
1	I_BIST_C	R/W1C	X	Indication of Built-In Self-Test complete: Write- 1-to-clear will clear the bit. The bit will be set again on completion of next BIST execution.Write- 1-to-clear will clear the bit. The bit will be set again on completion of next BIST execution. 0b = BIST not complete (or IEN_TEST.BIST_C is disabled) 1b = BIST complete
0	BIST	R/W1C	X	Built-In Self-Test fault: Write- 1-to-clear will clear the bit. The bit will be set again during next BIST execution if the same fault is detected. 0b = No BIST fault detected (or IEN_TEST.BIST is disabled) 1b = BIST fault detected

8.5.1.13 INT_VENDOR Register (Address = 0x24) [Default = X]

INT_VENDOR is shown in Table 8-18.

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This register contains various internal faults and ADDR detect pin fault.

Table 8-18 INT_VENDOR Register Field Descriptions

Bit	Field	Type	Default	Description
7	RSVD	R/W1C	X	RSVD
6	LDO_OV_Error	R/W1C	X	Internal LDO fault: 0 = No internal LDO fault detected 1 = Internal LDO fault detected Write- 1-to-clear will clear the bit.
5	RSVD	R/W1C	X	RSVD
4	Freq_DEV_Error	R/W1C	X	Internal Oscillator fault: 0 = No internal oscillator fault detected 1 = Internal oscillator fault detected Write- 1-to-clear will clear the bit.
3	SHORT_DET	R/W1C	X	Address Pin fault: 0 = No address pin fault detected 1 = Address pin fault detected Write- 1-to-clear will clear the bit.
2	OPEN_DET	R/W1C	X	Address Pin fault: 0 = No address pin fault detected 1 = Address pin fault detected Write- 1-to-clear will clear the bit.
1:0	RSVD	R/W1C	X	RSVD

8.5.1.14 VMON_STAT Register (Address = 0x30) [Default = X]

VMON_STAT is shown in Table 8-19.

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Status flags for internal operations and other non critical conditions. Status register showing completion of BIST, whether active or sleep or active/shutdown.

Table 8-19 VMON_STAT Register Field Descriptions

Bit	Field	Type	Default	Description
7	FAILSAFE	R	X	Fail Safe state: 0 = Not in Fail Safe state 1 = In Fail Safe state
6	ST_BIDT_C	R	X	Built-In Self-Test state: 0 = BIST not complete 1 = BIST complete
5	ST_VDD	R	X	Current state of VDD pin: 0 = VDD pin is low. 1 = VDD pin is high.
4	ST_NIRQ	R	X	Current state of NIRQ input: 0 = NIRQ pin driven low by system. 1 = NIRQ pin driven high by system.
3	ST_ACTSLP	R	X	Current state of SLEEP input: 0 = SLEEP pin driven low by system. 1 = SLEEP pin driven high by system.
2	ST_ACTSHDN	R	X	Current state of ACT input: 0 = ACT pin driven low by system. 1 = ACT pin driven high by system.
1	ST_SYNC	R	X	Current state of SYNC pin: 0 = SYNC pin is low. 1 = SYNC pin is high.
0	RSVD	R	X	RSVD

8.5.1.15 TEST_INFO Register (Address = 0x31) [Default = X]

TEST_INFO is shown in Table 8-20.

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Internal Self-Test and ECC information.

Table 8-20 TEST_INFO Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R	X	RSVD
5	ECC_SEC	R	X	Status of ECC single-error correction on OTP configuration load. 0 = no error correction applied 1 = single-error correction applied
4	ECC_DED	R	X	Status of ECC double-error detection on OTP configuration load. 0 = no double-error detected 1 = double-error detected
3	BIST_VM	R	X	Status of Volatile Memory test output from BIST. 0 = Volatile Memory test pass 1 = Volatile Memory test fail
2	BIST_NVM	R	X	Status of Non-Volatile Memory test output from BIST. 0 = Non-Volatile Memory test pass 1 = Non-Volatile Memory test fail
1	BIST_L	R	X	Status of Logic test output from BIST. 0 = Logic test pass 1 = Logic test fail
0	BIST_A	R	X	Status of Analog test output from BIST. 0 = Analog test pass 1 = Analog test fail

8.5.1.16 OFF_STAT Register (Address = 0x32) [Default = X]

OFF_STAT is shown in Table 8-21.

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Channel OFF status.

Table 8-21 OFF_STAT Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R	X	RSVD
5:0	VIN[N]	R	X	This register represents the OFF status of each channel: 0 = channel N is NOT OFF 1 = channel N is OFF (below OFF threshold)

8.5.1.17 SEQ_REC_STAT Register (Address = 0x34) [Default = X]

SEQ_REC_STAT is shown in Table 8-22.

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Sequence recording status register.

Table 8-22 SEQ_REC_STAT Register Field Descriptions

Bit	Field	Type	Default	Description
7	REC_ACTIVE	R	X	Indicates the status of sequence logging (recording): 0 = No sequence recording active. 1 = ACT or SLEEP or SEQ_REC_CTL.REC_START initiated a power sequence and recording is active.
6:5	SEQ	R	X	Current sequence being recorded: 00b = Power ON (ACT 01) 01b = Power OFF (ACT 10) 10b = Sleep Exit (SLEEP 01) 11b = Sleep Entry (SLEEP 10)
4	TS_RDY	R	X	Timestamp data availability in SEQ_TIME_xSB registers: If EN_TS_OW=0 this bit is cleared when TS_ACK is written to 1 by the host. If EN_TS_OW=1 this bit is cleared when all the SEQ_TIME_xSB[N] registers for the enabled channels (in VIN_CH_EN register) are read. If the bit is set and REC_ACTIVE is also set, then the data in SEQ_TIME_xSB registers is being overwritten. 0 = No new data available or data already read. 1 = New data available (data still needs to be read).
3	SEQ_ON_RDY	R	X	Power ON sequence data availability in SEQ_ON_LOG registers: If EN_SEQ_OW=0 this bit is cleared when SEQ_ON_ACK is written to 1 by the host. If EN_SEQ_OW=1 this bit is cleared when all the SEQ_ON_LOG registers for the enabled channels (in VIN_CH_EN register) are read. If the bit is set and REC_ACTIVE is set and SEQ [1:0]=00b, then the data in SEQ_ON_LOG registers is being overwritten. 0 = No new data available or data already read. 1 = New data available (data still needs to be read).
2	SEQ_OFF_RDY	R	X	Power OFF sequence data availability in SEQ_OFF_LOG registers: If EN_SEQ_OW=0 this bit is cleared when SEQ_OFF_ACK is written to 1 by the host. If EN_SEQ_OW=1 this bit is cleared when all the SEQ_OFF_LOG registers for the enabled channels (in VIN_CH_EN register) are read. If the bit is set and REC_ACTIVE is set and SEQ [1:0]=01b, then the data in SEQ_OFF_LOG registers is being overwritten. 0 = No new data available or data already read. 1 = New data available (data still needs to be read).
1	SEQ_EXS_RDY	R	X	Sleep Exit sequence data availability in SEQ_EXS_LOG registers: If EN_SEQ_OW=0 this bit is cleared when SEQ_EXS_ACK is written to 1 by the host. If EN_SEQ_OW=1 this bit is cleared when all the SEQ_EXS_LOG registers for the enabled channels (in VIN_CH_EN register) are read. If the bit is set and REC_ACTIVE is set and SEQ [1:0]=10b, then the data in SEQ_EXS_LOG registers is being overwritten. 0 = No new data available or data already read. 1 = New data available (data still needs to be read).
0	SEQ_ENS_RDY	R	X	Sleep Entry sequence data availability in SEQ_ENS_LOG registers: If EN_SEQ_OW=0 this bit is cleared when SEQ_ENS_ACK is written to 1 by the host. If EN_SEQ_OW=1 this bit is cleared when all the SEQ_ENS_LOG registers for the enabled channels (in VIN_CH_EN register) are read. If the bit is set and REC_ACTIVE is set and SEQ [1:0]=11b, then the data in SEQ_ENS_LOG registers is being overwritten. 0 = No new data available or data already read. 1 = New data available (data still needs to be read).

8.5.1.18 SEQ_OW_STAT Register (Address = 0x35) [Default = X]

SEQ_OW_STAT is shown in Table 8-23.

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Sequence recording overwrite status register.

Table 8-23 SEQ_OW_STAT Register Field Descriptions

Bit	Field	Type	Default	Description
7:5	RSVD	R	X	RSVD
4	TS_OW	R	X	Timestamp data overwritten status: 0 = No data was overwritten 1 = Data was overwritten (if VMON_MISC.EN_TS_OW=1), or data could not be written (if VMON_MISC.EN_TS_OW=0)
3	SEQ_ON_OW	R	X	Power ON sequence data overwritten status: 0 = No data was overwritten 1 = Data was overwritten (if VMON_MISC.EN_SEQ_OW=1), or data could not be written (if VMON_MISC.EN_SEQ_OW=0)
2	SEQ_OFF_OW	R	X	Power OFF sequence data overwritten status: 0 = No data was overwritten 1 = Data was overwritten (if VMON_MISC.EN_SEQ_OW=1), or data could not be written (if VMON_MISC.EN_SEQ_OW=0)
1	SEQ_EXS_OW	R	X	Sleep Exit sequence data overwritten status: 0 = No data was overwritten 1 = Data was overwritten (if VMON_MISC.EN_SEQ_OW=1), or data could not be written (if VMON_MISC.EN_SEQ_OW=0)
0	SEQ_ENS_OW	R	X	Sleep Entry sequence data overwritten status: 0 = No data was overwritten 1 = Data was overwritten (if VMON_MISC.EN_SEQ_OW=1), or data could not be written (if VMON_MISC.EN_SEQ_OW=0)

8.5.1.19 SEQ_ORD_STAT Register (Address = 0x36) [Default = X]

SEQ_ORD_STAT is shown in Table 8-24.

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Sequencing/SYNC counter (rail order) register value.

Table 8-24 SEQ_ORD_STAT Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	SYNC_COUNT[7:0]	R	X	This register represents the counter value during a power/sleep sequence. It corresponds to the number of SYNC falling edges detected, and used as tag value for monitored channels.

8.5.1.20 MON_LVL[1] Register (Address = 0x40) [Default = X]

MON_LVL[1] is shown in Table 8-25.

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For ADC readout -of each channel - 8bits

Table 8-25 MON_LVL[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ADC[7:0]	R	X	This register represents the 8-bit voltage level of channel 1. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling set to 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1LSB=5 mV. With scaling set to 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1LSB=20 mV.

8.5.1.21 MON_LVL[2] Register (Address = 0x41) [Default = X]

MON_LVL[2] is shown in Table 8-26.

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For ADC readout -of each channel - 8bits

Table 8-26 MON_LVL[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ADC[7:0]	R	X	This register represents the 8-bit voltage level of channel 2. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling set to 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1LSB=5 mV. With scaling set to 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1LSB=20 mV.

8.5.1.22 MON_LVL[3] Register (Address = 0x42) [Default = X]

MON_LVL[3] is shown in Table 8-27.

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For ADC readout -of each channel - 8bits

Table 8-27 MON_LVL[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ADC[7:0]	R	X	This register represents the 8-bit voltage level of channel 3. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling set to 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1LSB=5 mV. With scaling set to 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1LSB=20 mV.

8.5.1.23 MON_LVL[4] Register (Address = 0x43) [Default = X]

MON_LVL[4] is shown in Table 8-28.

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For ADC readout -of each channel - 8bits

Table 8-28 MON_LVL[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ADC[7:0]	R	X	This register represents the 8-bit voltage level of channel 4. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling set to 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1LSB=5 mV. With scaling set to 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1LSB=20 mV.

8.5.1.24 MON_LVL[5] Register (Address = 0x44) [Default = X]

MON_LVL[5] is shown in Table 8-29.

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For ADC readout -of each channel - 8bits

Table 8-29 MON_LVL[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ADC[7:0]	R	X	This register represents the 8-bit voltage level of channel 5. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling set to 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1LSB=5 mV. With scaling set to 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1LSB=20 mV.

8.5.1.25 MON_LVL[6] Register (Address = 0x45) [Default = X]

MON_LVL[6] is shown in Table 8-30.

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For ADC readout -of each channel - 8bits

Table 8-30 MON_LVL[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ADC[7:0]	R	X	This register represents the 8-bit voltage level of channel 6. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling set to 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1LSB=5 mV. With scaling set to 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1LSB=20 mV.

8.5.1.26 SEQ_ON_LOG[1] Register (Address = 0x50) [Default = X]

SEQ_ON_LOG[1] is shown in Table 8-31.

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Channel N Power ON sequence order value (ACT/ SLEEP 0 to 1).

Table 8-31 SEQ_ON_LOG[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Power ON sequence order value for channel 1. The sequence order value is the tag assigned to the channel during the sequence triggered by ACT. The tag is assigned when the voltage rising level passes the UV_LF[N] threshold. The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.27 SEQ_ON_LOG[2] Register (Address = 0x51) [Default = X]

SEQ_ON_LOG[2] is shown in Table 8-32.

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Channel N Power ON sequence order value (ACT/ SLEEP 0 to 1).

Table 8-32 SEQ_ON_LOG[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Power ON sequence order value for channel 2. The sequence order value is the tag assigned to the channel during the sequence triggered by ACT. The tag is assigned when the voltage rising level passes the UV_LF[N] threshold. The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.28 SEQ_ON_LOG[3] Register (Address = 0x52) [Default = X]

SEQ_ON_LOG[3] is shown in Table 8-33.

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Channel N Power ON sequence order value (ACT/ SLEEP 0 to 1).

Table 8-33 SEQ_ON_LOG[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Power ON sequence order value for channel 3. The sequence order value is the tag assigned to the channel during the sequence triggered by ACT. The tag is assigned when the voltage rising level passes the UV_LF[N] threshold. The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.29 SEQ_ON_LOG[4] Register (Address = 0x53) [Default = X]

SEQ_ON_LOG[4] is shown in Table 8-34.

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Channel N Power ON sequence order value (ACT/ SLEEP 0 to 1).

Table 8-34 SEQ_ON_LOG[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Power ON sequence order value for channel 4. The sequence order value is the tag assigned to the channel during the sequence triggered by ACT. The tag is assigned when the voltage rising level passes the UV_LF[N] threshold. The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.30 SEQ_ON_LOG[5] Register (Address = 0x54) [Default = X]

SEQ_ON_LOG[5] is shown in Table 8-35.

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Channel N Power ON sequence order value (ACT/ SLEEP 0 to 1).

Table 8-35 SEQ_ON_LOG[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Power ON sequence order value for channel 5. The sequence order value is the tag assigned to the channel during the sequence triggered by ACT. The tag is assigned when the voltage rising level passes the UV_LF[N] threshold. The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.31 SEQ_ON_LOG[6] Register (Address = 0x55) [Default = X]

SEQ_ON_LOG[6] is shown in Table 8-36.

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Channel N Power ON sequence order value (ACT/ SLEEP 0 to 1).

Table 8-36 SEQ_ON_LOG[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Power ON sequence order value for channel 6. The sequence order value is the tag assigned to the channel during the sequence triggered by ACT. The tag is assigned when the voltage rising level passes the UV_LF[N] threshold. The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.32 SEQ_OFF_LOG[1] Register (Address = 0x60) [Default = X]

SEQ_OFF_LOG[1] is shown in Table 8-37.

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Channel N Power OFF sequence order value (ACT 1 to 0).

Table 8-37 SEQ_OFF_LOG[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Power OFF sequence order value for channel 1. The sequence order value is the tag assigned to the channel during the sequence triggered by ACT. The tag is assigned when the voltage falling level passes the OFF threshold (200 mV). The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.33 SEQ_OFF_LOG[2] Register (Address = 0x61) [Default = X]

SEQ_OFF_LOG[2] is shown in Table 8-38.

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Channel N Power OFF sequence order value (ACT 1 to 0).

Table 8-38 SEQ_OFF_LOG[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Power OFF sequence order value for channel 2. The sequence order value is the tag assigned to the channel during the sequence triggered by ACT. The tag is assigned when the voltage falling level passes the OFF threshold (200 mV). The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.34 SEQ_OFF_LOG[3] Register (Address = 0x62) [Default = X]

SEQ_OFF_LOG[3] is shown in Table 8-39.

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Channel N Power OFF sequence order value (ACT 1 to 0).

Table 8-39 SEQ_OFF_LOG[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Power OFF sequence order value for channel 3. The sequence order value is the tag assigned to the channel during the sequence triggered by ACT. The tag is assigned when the voltage falling level passes the OFF threshold (200 mV). The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.35 SEQ_OFF_LOG[4] Register (Address = 0x63) [Default = X]

SEQ_OFF_LOG[4] is shown in Table 8-40.

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Channel N Power OFF sequence order value (ACT 1 to 0).

Table 8-40 SEQ_OFF_LOG[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Power OFF sequence order value for channel 4. The sequence order value is the tag assigned to the channel during the sequence triggered by ACT. The tag is assigned when the voltage falling level passes the OFF threshold (200 mV). The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.36 SEQ_OFF_LOG[5] Register (Address = 0x64) [Default = X]

SEQ_OFF_LOG[5] is shown in Table 8-41.

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Channel N Power OFF sequence order value (ACT 1 to 0).

Table 8-41 SEQ_OFF_LOG[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Power OFF sequence order value for channel 5. The sequence order value is the tag assigned to the channel during the sequence triggered by ACT. The tag is assigned when the voltage falling level passes the OFF threshold (200 mV). The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.37 SEQ_OFF_LOG[6] Register (Address = 0x65) [Default = X]

SEQ_OFF_LOG[6] is shown in Table 8-42.

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Channel N Power OFF sequence order value (ACT 1 to 0).

Table 8-42 SEQ_OFF_LOG[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Power OFF sequence order value for channel 6. The sequence order value is the tag assigned to the channel during the sequence triggered by ACT. The tag is assigned when the voltage falling level passes the OFF threshold (200 mV). The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.38 SEQ_EXS_LOG[1] Register (Address = 0x70) [Default = X]

SEQ_EXS_LOG[1] is shown in Table 8-43.

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Channel N Sleep Exit sequence order value (SLEEP 0 to 1).

Table 8-43 SEQ_EXS_LOG[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Sleep Exit sequence order value for channel 1. The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP. The tag is assigned when the voltage rising level passes the UV_LF[1] threshold. The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.39 SEQ_EXS_LOG[2] Register (Address = 0x71) [Default = X]

SEQ_EXS_LOG[2] is shown in Table 8-44.

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Channel N Sleep Exit sequence order value (SLEEP 0 to 1).

Table 8-44 SEQ_EXS_LOG[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Sleep Exit sequence order value for channel 2. The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP. The tag is assigned when the voltage rising level passes the UV_LF[2] threshold. The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.40 SEQ_EXS_LOG[3] Register (Address = 0x72) [Default = X]

SEQ_EXS_LOG[3] is shown in Table 8-45.

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Channel N Sleep Exit sequence order value (SLEEP 0 to 1).

Table 8-45 SEQ_EXS_LOG[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Sleep Exit sequence order value for channel 3. The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP. The tag is assigned when the voltage rising level passes the UV_LF[3] threshold. The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.41 SEQ_EXS_LOG[4] Register (Address = 0x73) [Default = X]

SEQ_EXS_LOG[4] is shown in Table 8-46.

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Channel N Sleep Exit sequence order value (SLEEP 0 to 1).

Table 8-46 SEQ_EXS_LOG[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Sleep Exit sequence order value for channel 4. The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP. The tag is assigned when the voltage rising level passes the UV_LF[4] threshold. The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.42 SEQ_EXS_LOG[5] Register (Address = 0x74) [Default = X]

SEQ_EXS_LOG[5] is shown in Table 8-47.

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Channel N Sleep Exit sequence order value (SLEEP 0 to 1).

Table 8-47 SEQ_EXS_LOG[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Sleep Exit sequence order value for channel 5. The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP. The tag is assigned when the voltage rising level passes the UV_LF[5] threshold. The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.43 SEQ_EXS_LOG[6] Register (Address = 0x75) [Default = X]

SEQ_EXS_LOG[6] is shown in Table 8-48.

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Channel N Sleep Exit sequence order value (SLEEP 0 to 1).

Table 8-48 SEQ_EXS_LOG[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Sleep Exit sequence order value for channel 6. The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP. The tag is assigned when the voltage rising level passes the UV_LF[6] threshold. The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.44 SEQ_ENS_LOG[1] Register (Address = 0x80) [Default = X]

SEQ_ENS_LOG[1] is shown in Table 8-49.

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Channel N Sleep Entry sequence order value (SLEEP 1 to 0).

Table 8-49 SEQ_ENS_LOG[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Sleep Entry sequence order value for channel 1. The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP. The tag is assigned when the voltage falling level passes the OFF threshold (200 mV). The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.45 SEQ_ENS_LOG[2] Register (Address = 0x81) [Default = X]

SEQ_ENS_LOG[2] is shown in Table 8-50.

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Channel N Sleep Entry sequence order value (SLEEP 1 to 0).

Table 8-50 SEQ_ENS_LOG[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Sleep Entry sequence order value for channel 2. The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP. The tag is assigned when the voltage falling level passes the OFF threshold (200 mV). The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.46 SEQ_ENS_LOG[3] Register (Address = 0x82) [Default = X]

SEQ_ENS_LOG[3] is shown in Table 8-51.

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Channel N Sleep Entry sequence order value (SLEEP 1 to 0).

Table 8-51 SEQ_ENS_LOG[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Sleep Entry sequence order value for channel 3. The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP. The tag is assigned when the voltage falling level passes the OFF threshold (200 mV). The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.47 SEQ_ENS_LOG[4] Register (Address = 0x83) [Default = X]

SEQ_ENS_LOG[4] is shown in Table 8-52.

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Channel N Sleep Entry sequence order value (SLEEP 1 to 0).

Table 8-52 SEQ_ENS_LOG[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Sleep Entry sequence order value for channel 4. The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP. The tag is assigned when the voltage falling level passes the OFF threshold (200 mV). The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.48 SEQ_ENS_LOG[5] Register (Address = 0x84) [Default = X]

SEQ_ENS_LOG[5] is shown in Table 8-53.

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Channel N Sleep Entry sequence order value (SLEEP 1 to 0).

Table 8-53 SEQ_ENS_LOG[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Sleep Entry sequence order value for channel 5. The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP. The tag is assigned when the voltage falling level passes the OFF threshold (200 mV). The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

8.5.1.49 SEQ_ENS_LOG[6] Register (Address = 0x85) [Default = X]

SEQ_ENS_LOG[6] is shown in Table 8-54.

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Channel N Sleep Entry sequence order value (SLEEP 1 to 0).

Table 8-54 SEQ_ENS_LOG[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R	X	This register stores the Sleep Entry sequence order value for channel 6. The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP. The tag is assigned when the voltage falling level passes the OFF threshold (200 mV). The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.