JAJSQG3B march 2022 – may 2023 TPS389006-Q1
PRODUCTION DATA
Built-In Self Test (BIST) is performed:
Configuration load from OTP is assisted by ECC (supporting SEC-DED). This is to protect against data integrity issues and to maximize system availability.
During BIST, NIRQ is de-asserted (asserted in case of failure), input pins are ignored, SYNC is tri-stated, and the I2C block is inactive with SDA and SCL de-asserted. The BIST includes device testing to meet the Functional Safety goals outlined in functional safety documentation. Once BIST is completed without failure, I2C is immediately active and the device enters the IDLE sate after loading the configuration data from OTP. If BIST fails and/or ECC reports Double-Error Detection (DED; meant for detecting multiple bit flips when loading data from memory), NIRQ is asserted, the device enters FAILSAFE state, and a best effort attempt is made to keep the I2C function active. TEST_INFO register may provide additional information on the test results.
The detailed behavior upon success/failure of the BIST is controlled by INT_TEST and IEN_TEST registers. Reporting of the BIST results is carried out through: