JAJSLH4B April   2021  – January 2024 TPS3899-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Nomenclature
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD Hysteresis
      2. 7.3.2 User-Programmable Sense and Reset Time Delay
      3. 7.3.3 RESET/RESET Output
      4. 7.3.4 SENSE Input
        1. 7.3.4.1 Immunity to SENSE Pin Voltage Transients
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 7.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Timing Diagrams

GUID-20210305-CA0I-RH4P-7R14-KP1F9PBCG6L2-low.svg

(1) tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to the CTR pin then tD programmed time
is added to the startup time.

(2) Be advised, in some instances, the VDD falling slew rate in Figure 6-1 can be slow or such that VDD decay time is much larger than the SENSE
delay time (tD-SENSE) time allowing the output to assert. If the VDD falling slew rate is much faster than the (tD-SENSE), the output appears to be not
asserted.

Figure 6-1 TPS3899DL01-Q1 and TPS3899PL01-Q1 Timing Diagram






GUID-20210305-CA0I-3RZ4-B6NW-S3CDJNC8BHW8-low.svg

(1) tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to the CTR pin then tD programmed time
is added to the startup time.

(2) Be advised, in some instances, that the VDD falling slew rate in Figure 6-2 can be slow or such that VDD decay time is much larger than the SENSE
delay time (tD-SENSE) time allowing the output to assert. If the VDD falling slew rate is much faster than the (tD-SENSE), the output appears to be not
asserted.

Figure 6-2 TPS3899PH01-Q1 Timing Diagram