JAJSOH5D November 2022 – November 2023 TPS389C03-Q1
PRODUCTION DATA
Table 8-1 lists the memory-mapped registers for the BANK0 registers. All register offset addresses not listed in Table 8-1 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 10h | INT_SRC | Global Interrupt Source Status register. | Go |
| 11h | INT_MONITOR | Voltage Monitor Interrupt Status register. | Go |
| 12h | INT_UVHF | High Frequency channel Under-Voltage Interrupt Status register. | Go |
| 14h | INT_UVLF | Low Frequency channel Under-Voltage Interrupt Status register. | Go |
| 16h | INT_OVHF | High Frequency channel Over-Voltage Interrupt Status register | Go |
| 18h | INT_OVLF | Low Frequency channel Over-Voltage Interrupt Status register | Go |
| 22h | INT_CONTROL | Control and Communication Interrupt Status register. | Go |
| 23h | INT_TEST | Internal Test and Configuration Load Interrupt Status register. | Go |
| 24h | INT_VENDOR | Vendor Specific Internal Interrupt Status register. | Go |
| 30h | VMON_STAT | Status flags for internal operations and other non critical conditions. | Go |
| 31h | TEST_INFO | Internal Self-Test and ECC information. | Go |
| 32h | OFF_STAT | Channel OFF status. | Go |
| 37h | WDT_STAT | Watchdog Status | Go |
| 38h | WD_STAT_QA | Watchdog Answer Count and Token | Go |
| 41h | MON_LVL[2] | Channel 2 voltage level. | Go |
| 42h | MON_LVL[3] | Channel 3 voltage level. | Go |
| 43h | MON_LVL[4] | Channel 4 voltage level. | Go |
| F0h | BANK_SEL | Bank Select. | Go |
| F1h | PROT1 | Locks or unlocks register changes. Must match PROT2. | Go |
| F2h | PROT2 | Locks or unlocks register changes. Must match PROT1. | Go |
| F3h | PROT_MON | Locks MON registers in tandem with PROT1 and PROT2. | Go |
| F9h | I2CADDR | I2C Address | Go |
| FAh | DEV_CFG | Status of I2C interface voltage levels. | Go |
Complex bit access types are encoded to fit into small table cells. Table 8-2 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | W 1C | Write 1 to clear |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
INT_SRC is shown in Table 8-3.
Return to the Summary Table.
Global Interrupt Source Status register.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | F_OTHER | R | 0h | Vendor internal defined faults. Details reported in INT_Vendor. Represents ORed value of all bits in INT_Vendor. 0 = No Vendor defined faults detected 1 = Vendor defined faults detected |
| 6-3 | RSVD | R | 0h | RSVD |
| 2 | TEST | R | 0h | Internal test or configuration load fault. Details reported in INT_TEST. Represents ORed value of all bits in INT_TEST. 0 = No test/configuration fault detected 1 = Test/configuration fault detected |
| 1 | CONTROL | R | 0h | Control status or communication fault. Details reported in INT_CONTROL. Represents ORed value of all bits in INT_CONTROL. 0 = No status or communication fault detected 1 = Status or communication fault detected |
| 0 | MONITOR | R | 0h | Voltage monitor fault. Details reported in INT_MONITOR. Represents ORed value of all bits in INT_MONITOR. 0 = No voltage fault detected 1 = Voltage fault detected |
INT_MONITOR is shown in Table 8-4.
Return to the Summary Table.
Voltage Monitor Interrupt Status register.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RSVD | R | 0h | RSVD |
| 3 | OVLF | R | 0h | Over-Voltage Low Frequency Fault reported by ADC based measurement. Details reported in INT_OVLF. Represents ORed value of all bits in INT_OVLF. 0 = No OVLF fault detected 1 = OVLF fault detected |
| 2 | OVHF | R | 0h | Over-Voltage High Frequency Fault reported by comparator based monitoring. Details reported in INT_OVHF. Represents ORed value of all bits in INT_OVHF. 0 = No OVHF fault detected 1 = OVHF fault detected |
| 1 | UVLF | R | 0h | Under-Voltage Low Frequency Fault reported by ADC based measurement. Details reported in INT_UVLF. Represents ORed value of all bits in INT_UVLF. 0 = No UVLF fault detected 1 = UVLF fault detected |
| 0 | UVHF | R | 0h | Under-Voltage High Frequency Fault reported by comparator based monitoring. Details reported in INT_UVHF. Represents ORed value of all bits in INT_UVHF. 0 = No UVHF fault detected 1 = UVHF fault detected |
INT_UVHF is shown in Table 8-5.
Return to the Summary Table.
High Frequency channel Under-Voltage Interrupt Status register.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RSVD | R/W1C | 0h | RSVD |
| 3 | F_UVHF[4] | R/W1C | 0h | Under-Voltage High Frequency Fault for MON4. Trips if MON4 High Frequency signal goes below UVHF[4]. 0 = MON4 has no UVHF fault detected (or interrupt disabled in IEN_UVHF register) 1 = MON4 has UVHF fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the UVHF fault condition is also removed (MON4 High Frequency signal is above UVHF[4]). |
| 2 | F_UVHF[3] | R/W1C | 0h | Under-Voltage High Frequency Fault for MON3. Trips if MON3 High Frequency signal goes below UVHF[3]. 0 = MON3 has no UVHF fault detected (or interrupt disabled in IEN_UVHF register) 1 = MON3 has UVHF fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the UVHF fault condition is also removed (MON3 High Frequency signal is above UVHF[3]). |
| 1 | F_UVHF[2] | R/W1C | 0h | Under-Voltage High Frequency Fault for MON2. Trips if MON2 High Frequency signal goes below UVHF[2]. 0 = MON2 has no UVHF fault detected (or interrupt disabled in IEN_UVHF register) 1 = MON2 has UVHF fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the UVHF fault condition is also removed (MON2 High Frequency signal is above UVHF[2]). |
| 0 | RSVD | R/W1C | 0h | RSVD |
INT_UVLF is shown in Table 8-6.
Return to the Summary Table.
Low Frequency channel Under-Voltage Interrupt Status register.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RSVD | R/W1C | 0h | RSVD |
| 3 | F_UVLF[4] | R/W1C | 0h | Under-Voltage Low Frequency Fault for MON4 . Trips if MON4 Low Frequency signal goes below UVLF[4]. 0 = MON4 has no UVLF fault detected (or interrupt disabled in IEN_UVLF register) 1 = MON4 has UVLF fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the UVLF fault condition is also removed (MON4 Low Frequency signal is above UVLF[4]). |
| 2 | F_UVLF[3] | R/W1C | 0h | Under-Voltage Low Frequency Fault for MON3. Trips if MON3 Low Frequency signal goes below UVLF[3]. 0 = MON3 has no UVLF fault detected (or interrupt disabled in IEN_UVLF register) 1 = MON3 has UVLF fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the UVLF fault condition is also removed (MON3 Low Frequency signal is above UVLF[3]). |
| 1 | F_UVLF[2] | R/W1C | 0h | Under-Voltage Low Frequency Fault for MON2. Trips if MON2 Low Frequency signal goes below UVLF[2]. 0 = MON2 has no UVLF fault detected (or interrupt disabled in IEN_UVLF register) 1 = MON2 has UVLF fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the UVLF fault condition is also removed (MON2 Low Frequency signal is above UVLF[2]). |
| 0 | RSVD | R/W1C | 0h | RSVD |
INT_OVHF is shown in Table 8-7.
Return to the Summary Table.
High Frequency channel Over-Voltage Interrupt Status register
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RSVD | R/W1C | 0h | RSVD |
| 3 | F_OVHF[4] | R/W1C | 0h | Over-Voltage High Frequency Fault for MON4. Trips if MON4 High Frequency signal goes above OVHF[4]. 0 = MON4 has noOVHF fault detected (or interrupt disabled in IEN_OVHF register) 1 = MON4 has OVHF fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the OVHF fault condition is also removed (MON4 High Frequency signal is below OVHF[4]) |
| 2 | F_OVHF[3] | R/W1C | 0h | Over-Voltage High Frequency Fault for MON3. Trips if MON3 High Frequency signal goes above OVHF[3]. 0 = MON3 has no OVHF fault detected (or interrupt disabled in IEN_OVHF register) 1 = MON3 has OVHF fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the OVHF fault condition is also removed (MON3 High Frequency signal is below OVHF[3]) |
| 1 | F_OVHF[2] | R/W1C | 0h | Over-Voltage High Frequency Fault for MON2. Trips if MON2 High Frequency signal goes above OVHF[2]. 0 = MON2 has no OVHF fault detected (or interrupt disabled in IEN_OVHF register) 1 = MON2 has OVHF fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the OVHF fault condition is also removed (MON2 High Frequency signal is below OVHF[2]) |
| 0 | RSVD | R/W1C | 0h | RSVD |
INT_OVLF is shown in Table 8-8.
Return to the Summary Table.
Low Frequency channel Over-Voltage Interrupt Status register
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RSVD | R/W1C | 0h | RSVD |
| 3 | F_OVLF[4] | R/W1C | 0h | Over-Voltage Low Frequency Fault for MON4. Trips if MON4 Low Frequency signal goes above OVLF[4]. 0 = MON4 has no OVLF fault detected (or interrupt disabled in IEN_OVLF register) 1 = MON4 has OVLF fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the OVLF fault condition is also removed (MON4 Low Frequency signal is below OVLF[4]). |
| 2 | F_OVLF[3] | R/W1C | 0h | Over-Voltage Low Frequency Fault for MON3. Trips if MON3 Low Frequency signal goes above OVLF[3]. 0 = MON3 has no OVLF fault detected (or interrupt disabled in IEN_OVLF register) 1 = MON3 has OVLF fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the OVLF fault condition is also removed (MON3 Low Frequency signal is below OVLF[3]). |
| 1 | F_OVLF[2] | R/W1C | 0h | Over-Voltage Low Frequency Fault for MON2. Trips if MON2 Low Frequency signal goes above OVLF[2]. 0 = MON2 has no OVLF fault detected (or interrupt disabled in IEN_OVLF register) 1 = MON2 has OVLF fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the OVLF fault condition is also removed (MON2 Low Frequency signal is below OVLF[2]). |
| 0 | RSVD | R/W1C | 0h | RSVD |
INT_CONTROL is shown in Table 8-9.
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Control and Communication Interrupt Status register.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | RSVD | R/W1C | 0h | RSVD |
| 4 | F_CRC | R/W1C | 0h | Runtime register CRC Fault: 0 = No fault detected (or IEN_CONTROL.RT_CRC is disabled) 1 = Register CRC fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit. The bit will be set again during next register CRC check if the same fault is detected |
| 3 | F_NIRQ | R/W1C | 0h | Interrupt pin fault (fault bit always enabled; no enable bit available): 0 = No fault detected on NIRQ pin 1 = Low resistance path to supply detected on NIRQ pin The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the NIRQ fault condition is also removed. |
| 2 | F_TSD | R/W1C | 0h | Thermal Shutdown fault: 0 = No TSD fault detected (or IEN_CONTROL.TSD is disabled) 1 = TSD fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the TSD fault condition is also removed |
| 1 | RSVD | R/W1C | 0h | RSVD |
| 0 | F_PEC | R/W1C | 0h | Packet Error Checking fault: 0 = PEC mismatch has not occurred (or IEN_CONTROL.PEC is disabled) 1 = PEC mismatch has occurred, or VMON_MISC.REQ_PEC=1 and PEC is missing in a write transaction The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit. The bit will be set again during next I2C transaction if the same fault is detected. |
INT_TEST is shown in Table 8-10.
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Internal Test and Configuration Load Interrupt Status register.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RSVD | R/W1C | 0h | RSVD |
| 3 | ECC_SEC | R/W1C | 0h | ECC single-error corrected on OTP configuration load: 0 = No single-error corrected (or IEN_TEST.ECC_SEC is disabled) 1 = Single-error corrected Write-1-to-clear will clear the bit. The bit will be set again during next OTP configuration load if the same fault is detected. |
| 2 | ECC_DED | R/W1C | 0h | ECC double-error detected on OTP configuration load: 0 = No double-error detected on OTP load 1 = Double-error detected on OTP load The fault bit is always enabled (there is no associated interrupt enable bit). The device will move to failsafe mode on double error detection. |
| 1 | BIST_Complete_INT | R/W1C | 0h | Indication of Built-In Self-Test complete: 0 = BIST not complete (or IEN_TEST.BIST_C is disabled) 1 = BIST complete Write-1-to-clear will clear the bit. The bit will be set again on completion of next BIST execution |
| 0 | BIST_Fail_INT | R/W1C | 0h | Built-In Self-Test fault: 0 = No BIST fault detected (or IEN_TEST.BIST is disabled) 1 = BIST fault detected Write-1-to-clear will clear the bit. The bit will be set again during next BIST execution if the fault is detected |
INT_VENDOR is shown in Table 8-11.
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Vendor Specific Internal Interrupt Status register.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RSVD | R/W1C | 0h | RSVD |
| 6 | LDO_OV_Error | R/W1C | 0h | Internal LDO Overvoltage error. 0 = No internal LDO overvoltage fault detected 1 = Internal LDO overvoltage fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the LDO fault condition is also removed. |
| 5 | NRST_MISMATCH | R/W1C | 0h | Designates error due to drive state and read back. During an NRST toggle NRST mismatch will be active after 2µs, NRST must exceed 0.6*VDD to be considered in a logic high state. 0 = No fault detected on NRST pin 1 = Error due to drive state and read back. The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the NRST fault condition is also removed. |
| 4 | Freq_DEV_Error | R/W1C | 0h | Designates internal frequency errors. 0 = No internal frequency fault detected 1 = Internal frequency fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the frequency fault condition is also removed. |
| 3 | SHORT_DET | R/W1C | 0h | Address pin short detect. 0 = No address pin short fault detected 1 = Address pin short fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the address pin short fault condition is also removed. |
| 2 | OPEN_DET | R/W1C | 0h | Address pin open detect. 0 = No address pin open fault detected 1 = Address pin open fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the address pin open fault condition is also removed. |
| 1 | ESM_ERROR | R/W1C | 0h | Indication of ESM fault. 0 = No ESM fault detected 1 = ESM fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the ESM fault condition is also removed. |
| 0 | WDT_ERROR | R/W1C | 0h | Indication of Watchdog fault. 0 = No Watchdog fault detected 1 = Watchdog fault detected The recovery of the fault condition does NOT clear the bit. It can only be cleared by the host with a write-1-to-clear. Write-1-to-clear will clear the bit only if the Watchdog fault condition is also removed. |
VMON_STAT is shown in Table 8-12.
Return to the Summary Table.
Status flags for internal operations and other non critical conditions.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | FAILSAFE | R | 0h | 1 = Device in FAILSAFE state |
| 6 | ST_BIST_C | R | 1h | Built-In Self-Test state: 0 = BIST not complete 1 = BIST complete |
| 5 | ST_VDD | R | 1h | Status VDD |
| 4 | ST_NIRQ | R | 1h | Status NIRQ pin |
| 3 | RSVD | R | 1h | RSVD |
| 2 | ACTIVE | R | 1h | 1 = Device in ACTIVE state |
| 1 | RSVD | R | 1h | RSVD |
| 0 | RSVD | R | 0h | RSVD |
TEST_INFO is shown in Table 8-13.
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Internal Self-Test and ECC information.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RSVD | R | 0h | RSVD |
| 5 | ECC_SEC | R | 0h | Status of ECC single-error correction on OTP configuration load. 0 = no error correction applied 1 = single-error correction applied |
| 4 | ECC_DED | R | 0h | Status of ECC double-error detection on OTP configuration load. 0 = no double-error detected 1 = double-error detected |
| 3 | BIST_VM | R | 0h | Status of Volatile Memory test output from BIST. 0 = Volatile Memory test pass 1 = Volatile Memory test fail |
| 2 | BIST_NVM | R | 0h | Status of Non-Volatile Memory test output from BIST. 0 = Non-Volatile Memory test pass 1 = Non-Volatile Memory test fail |
| 1 | BIST_L | R | 0h | Status of Logic test output from BIST. 0 = Logic test pass 1 = Logic test fail |
| 0 | BIST_A | R | 0h | Status of Analog test output from BIST. 0 = Analog test pass 1 = Analog test fail |
OFF_STAT is shown in Table 8-14.
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Channel OFF status.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RSVD | R | 0h | RSVD |
| 3 | MON[4] | R | 0h | Represents the OFF status of each channel: 0 = channel 4 is NOT OFF 1 = channel 4 is OFF (below OFF threshold) |
| 2 | MON[3] | R | 0h | Represents the OFF status of each channel: 0 = channel 3 is NOT OFF 1 = channel 3 is OFF (below OFF threshold) |
| 1 | MON[2] | R | 0h | Represents the OFF status of each channel: 0 = channel 2 is NOT OFF 1 = channel 2 is OFF (below OFF threshold) |
| 0 | RSVD | R | 0h | RSVD |
WDT_STAT is shown in Table 8-15.
Return to the Summary Table.
Watchdog Status
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RSVD | R | 0h | RSVD |
| 5-3 | WD_STATE | R | 0h | Represents Watchdog state. 000 = WD Idle state 001 = WD Open state 010 = WD Close state 011 = WD Startup state 100 = WD suspend state |
| 2 | ST_WDEXP | R | 0h | Will flag if close window expires before writing 3 answers or if open window expires. 1 = close window or open window expired (bit clears when read) |
| 1 | RSVD | R | 0h | RSVD |
| 0 | ST_WDUV | R | 0h | Will flag if an extra answer in close window (4 answers in close window) OR a wrong answer in close window OR a wrong answer in open window. 1 = extra or wrong answer (bit clears when read) |
WD_STAT_QA is shown in Table 8-16.
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Watchdog Answer Count and Token
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RSVD | R | 0h | RSVD |
| 5-4 | ANSW_CNT[1:0] | R | 3h | Represents Answer count in real time |
| 3-0 | TOKEN[3:0] | R | Ch | Represents Token in real time. Enabling the watchdog sets the Token value to 0. |
MON_LVL[2] is shown in Table 8-17.
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Channel 2 voltage level.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ADC[7:0] | R | 0h | Represents MON2 voltage telemetry value in hex |
MON_LVL[3] is shown in Table 8-18.
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Channel 3 voltage level.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ADC[7:0] | R | 0h | Represents MON3 voltage telemetry value in hex |
MON_LVL[4] is shown in Table 8-19.
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Channel 4 voltage level.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ADC[7:0] | R | 0h | Represents MON4 voltage telemetry value in hex |
BANK_SEL is shown in Table 8-20.
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Bank Select.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-1 | RSVD | R/W | 0h | RSVD |
| 0 | BANK_Select | R/W | 0h | Represents bank selection. 0 = Bank 0 1 = Bank 1 |
PROT1 is shown in Table 8-21.
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Locks or unlocks register changes. Must match PROT2.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RSVD | R/W | 0h | RSVD |
| 5 | WRKC | R/W | 0h | Represents Protection from writes for WRKC group. Both PROT1 and PROT2 need to be set for protection. 0 = Changes to register are possible 1 = Changes to register are not possible |
| 4 | RSVD | R/W | 0h | RSVD |
| 3 | CFG | R/W | 0h | Represents Protection from writes for CFG group. Both PROT1 and PROT2 need to be set for protection. 0 = Changes to register are possible 1 = Changes to register are not possible |
| 2 | IEN | R/W | 0h | Represents Protection from writes for IEN group. Both PROT1 and PROT2 need to be set for protection. 0 = Changes to register are possible 1 = Changes to register are not possible |
| 1 | MON | R/W | 0h | Represents Protection from writes for MON group. Both PROT1 and PROT2 need to be set for protection. 0 = Changes to register are possible 1 = Changes to register are not possible |
| 0 | RSVD | R/W | 0h | RSVD |
PROT2 is shown in Table 8-22.
Return to the Summary Table.
Locks or unlocks register changes. Must match PROT1.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RSVD | R/W | 0h | RSVD |
| 5 | WRKC | R/W | 0h | Represents Protection from writes for CFG group. Both PROT1 and PROT2 need to be set for protection. 0 = Changes to register are possible 1 = Changes to register are not possible |
| 4 | RSVD | R/W | 0h | RSVD |
| 3 | CFG | R/W | 0h | Represents Protection from writes for CFG group. Both PROT1 and PROT2 need to be set for protection. 0 = Changes to register are possible 1 = Changes to register are not possible |
| 2 | IEN | R/W | 0h | Represents Protection from writes for IEN group. Both PROT1 and PROT2 need to be set for protection. 0 = Changes to register are possible 1 = Changes to register are not possible |
| 1 | MON | R/W | 0h | Represents Protection from writes for MON group. Both PROT1 and PROT2 need to be set for protection. 0 = Changes to register are possible 1 = Changes to register are not possible |
| 0 | RSVD | R/W | 0h | RSVD |
PROT_MON is shown in Table 8-23.
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Locks MON registers in tandem with PROT1 and PROT2.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RSVD | R/W | 1h | RSVD |
| 3 | MON[4] | R/W | 1h | Protects MON4 from writes along with PROT1 and PROT2. 0= Changes are possible 1= Changes are not possible |
| 2 | MON[3] | R/W | 1h | Protects MON3 from writes along with PROT1 and PROT2. 0= Changes are possible 1= Changes are not possible |
| 1 | MON[2] | R/W | 1h | Protects MON2 from writes along with PROT1 and PROT2. 0= Changes are possible 1= Changes are not possible |
| 0 | RSVD | R/W | 1h | RSVD |
I2CADDR is shown in Table 8-24.
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I2C Address
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RSVD | R/W | 0h | RSVD |
| 6-3 | ADDR_NVM[3:0] | R | 6h | Represents I2C address from internal OTP. Default value of 30 hex. Also the default I2C address for fail safe mode if I2C communication fails |
| 2-0 | ADDR_STRAP[2:0] | R | 0h | Represents I2C address from resistor value on ADDR pin. |
DEV_CFG is shown in Table 8-25.
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Status of I2C interface voltage levels.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | RSVD | R | 0h | RSVD |