JAJSOH5D November 2022 – November 2023 TPS389C03-Q1
PRODUCTION DATA
TPS389C03-Q1 supports Packet Error Checking (PEC) as a way to implement Cyclic Redundancy Checking (CRC). With the initial value of CRC set to 0x00, the PEC uses a CRC-8 represented by the polynomial:
The PEC calculation includes all bytes in the transmission, including address, command and data. The PEC calculation does not include ACK or NACK bits or START, STOP or REPEATED START conditions. If PEC is enabled, and the TPS389C03-Q1 is transmitting data, then the TPS389C03-Q1 is responsible for sending the PEC byte. If PEC is enabled, and the TPS389C03-Q1 is reveiving data from the MCU, then the MCU is responsible for sending the PEC byte.
If PEC is enabled by EN_PEC, and the PEC byte is present in the write transaction, the device will NACK and assert NIRQ if PEC byte is incorrect.
If PEC is enabled by EN_PEC, and the PEC byte is not present in the write transaction.
If REQ_PEC = 0, missing PEC is treated as good PEC and register write succeeds. NIRQ is not asserted.
If REQ_PEC = 1, missing PEC is treated as incorrect PEC and register write fails. NIRQ is asserted.