JAJSOH5D November   2022  – November 2023 TPS389C03-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Maskable Interrupt (AMSK)
      3. 7.3.3  VDD
      4. 7.3.4  MON
      5. 7.3.5  NRST
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Packet Error Checking (PEC)
      9. 7.3.9  Q&A Watchdog
        1. 7.3.9.1 Question and Token Generation
        2. 7.3.9.2 Q&A Watchdog Open and Close Window Delay
        3. 7.3.9.3 Q&A Watchdog Status Register
        4. 7.3.9.4 Q&A Watchdog Timing
        5. 7.3.9.5 Q&A Watchdog State Machine and Test Program
      10. 7.3.10 Error Signal Monitoring (ESM)
        1. 7.3.10.1 ESM Timing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389C03-Q1 Power ON
  9. 8 Register Maps
    1. 8.1 Registers Overview
      1. 8.1.1 BANK0 Registers
      2. 8.1.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Guidelines
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Documentation Support
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

At 2.6 V ≤ VDD≤ 5.5 V, NIRQ Voltage = 10 kΩ to VDD, NIRQ load = 10 pF, and over the operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical conditions at VDD= 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON PARAMETERS
VDD Input supply voltage  2.6 5.5 V
VDDUVLO Rising Threshold 2.67 2.81 V
Falling Threshold 2.48 2.6 V
VPOR Power on Reset Voltage (2) 1.65 V
IDD_Active Supply current into VDD pin 

 		 VDD≤5.5V  1550 2000 µA
VMONX MON voltage range 0.2 5.5 V
IMONX Input current MONx pins VMON=5V 20 µA
VMON_LF 1x mode (No scaling) 0.2 1.475 V
 4x mode 0.8 5.5 V
VMON_HF 1x mode (No scaling) 0.2 1.475 V
 4x mode 0.8 5.5 V
Threshold Granularity_LF 1x mode (No scaling)  5 mV
4x mode  20 mV
Threshold Granularity_HF 1x mode (No scaling)  5 mV
Threshold Granularity_HF 4x mode  20 mV
Accuracy_HF VMON 0.2V≤VMONX≤1.0V –6 6 mV
1.0V<VMONX≤1.475V  -7.5 7.5 mV
1.475V<VMONX≤2.95V  -0.6 0.6 %
VMONX>2.95V  -0.7 0.7 %
VHYS_HF Hysteresis on UV,OV pin(Hysteresis is with respect of the tripoint ((UV),(OV))(1) 0.2V≤VMONX≤1.475V 5 11 mV
1.475V<VMONX≤2.95V 9 16
VMONX>2.95V 17 28 mV
MON_OFF OFF Voltage threshold Monitored falling edge of VMON 140 215 mV
NIRQ On resistance- when asserted Low Open Drain  12 17 Ω
VOL Low level output voltage-NIRQ NIRQ, 5.5V/5mA 100 mV
Ilkg(OD) Open-Drain output leakage current-NIRQ NIRQ pin in High Impedance,VNIRQ= 5.5, Not asserted 90 nA
NRST On resistance- when asserted Low  Open Drain 10 15 Ω
VOL Low level output voltage-NRST NRST , 5.5V/5mA 100 mV
Ilkg(OD) Open-Drain output leakage current-NRST NRST pin in High Impedance,VNRST= 5.5, Not asserted 600 nA
WDO On resistance- when asserted Low  Open Drain 12 17 Ω
VOL Low level output voltage-WDO WDO  , 5.5V/5mA 100 mV
Ilkg(OD) Open-Drain output leakage current-WDO WDO pin in High Impedance,VNRST= 5.5, Not asserted 500 nA
ESM_L Logic Low Input 0.24 x VDD V
ESM_H Logic High Input VDD>4.5 0.55 x VDD V
VDD<4.5 0.6 x VDD V
Ilkg(ESM) Leakage current ESM=5.5V 75 µA
WDE_L Logic Low Input 0.36 V
WDE_H Logic High Input 1.26 V
Ilkg(WDE) Leakage current WDE=5.5V 5 µA
IADDR ADDR pin current 20 µA
I2C ADDR (Hex format) R=5.36k 0x30
R=16.2k 0x31
R=26.7k 0x32
R=37.4k 0x33
R=47.5k 0x34
R=59.0k 0x35
R=69.8k 0x36
R=80.6k 0x37
TSD Thermal Shutdown 155 ℃
TSD Hys Thernal Shutdown Hysterisis 25 ℃
RS Remote sense range -100 100 mV
ADC SPECIFICATION
Vin Input Range 0.2 5.5 V
Resolution 1x mode 0.2V≤VMON≤1.475V 5 mV
4x mode VMON>1.475V 20 mV
fS Sample Rate 125 ksps
Accuracy_LF VMON,1x mode 0.2V≤VMON≤1.475V -12 +12 mV
VMON, 4x mode VMON>1.475V -40 +40 mV
I2C ELECTRICAL SPECIFICATIONS
VHYS_LF Hysteresis LF Faults, 1x mode 0.2V≤VMON≤1.475V 10 15 mV
Hysteresis LF Faults, 4x mode VMON>1.475V 40 55 mV
CB Capacitive load for SDA and SCL 400 pF
SDA,SCL Low Threshold DEV_CONFIG.SOC_IF=0 0.84 V
SDA,SCL High Threshold DEV_CONFIG.SOC_IF=0 2.31 V
(1) Hysteresis is with respect of the tripoint (VIT-(UV), VIT+(OV)).
(2) VPOR is the minimum VDDX voltage level for a controlled output state.