JAJSRX9C January   2012  – November 2023 TPS40170-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  LDO Linear Regulators and Enable
      2. 6.3.2  Input Undervoltage Lockout (UVLO)
      3. 6.3.3  Equations for Programming the Input UVLO
      4. 6.3.4  Overcurrent Protection and Short-Circuit Protection (OCP and SCP)
      5. 6.3.5  Oscillator and Voltage Feed-Forward
        1. 6.3.5.1 Calculating the Timing Resistance (RRT)
      6. 6.3.6  Feed-Forward Oscillator Timing Diagram
      7. 6.3.7  Soft-Start and Fault-Logic
        1. 6.3.7.1 Soft-Start During Overcurrent Fault
        2. 6.3.7.2 Equations for Soft-Start and Restart Time
      8. 6.3.8  Overtemperature Fault
      9. 6.3.9  Tracking
      10. 6.3.10 Adaptive Drivers
      11. 6.3.11 Start-Up Into Pre-Biased Output
      12. 6.3.12 31
      13. 6.3.13 Power Good (PGOOD)
      14. 6.3.14 PGND and AGND
      15. 6.3.15 Bootstrap Capacitor
      16. 6.3.16 Bypass and Filtering
    4. 6.4 Device Functional Modes
      1. 6.4.1 Frequency Synchronization
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Select A Switching Frequency
        2. 7.2.2.2  Inductor Selection (L1)
        3. 7.2.2.3  Output Capacitor Selection (C9)
        4. 7.2.2.4  Peak Current Rating of Inductor
        5. 7.2.2.5  Input Capacitor Selection (C1, C6)
        6. 7.2.2.6  MOSFET Switch Selection (Q1, Q2)
        7. 7.2.2.7  Timing Resistor (R7)
        8. 7.2.2.8  UVLO Programming Resistors (R2, R6)
        9. 7.2.2.9  Bootstrap Capacitor (C7)
        10. 7.2.2.10 VIN Bypass Capacitor (C18)
        11. 7.2.2.11 VBP Bypass Capacitor (C19)
        12. 7.2.2.12 SS Timing Capacitor (C15)
        13. 7.2.2.13 ILIM Resistor (R19, C17)
        14. 7.2.2.14 SCP Multiplier Selection (R5)
        15. 7.2.2.15 Feedback Divider (R10, R11)
        16. 7.2.2.16 Compensation: (R4, R13, C13, C14, C21)
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bootstrap Resistor
      2. 7.3.2 SW-Node Snubber Capacitor
      3. 7.3.3 Input Resistor
      4. 7.3.4 LDRV Gate Capacitor
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.7 Soft-Start and Fault-Logic

A capacitor from the SS pin to GND defines the SS time, tSS. The TPS40170-Q1 device enters into soft-start immediately after completion of the overcurrent calibration. The SS pin goes through the internal level-shifter circuit of the device before reaching one of the positive inputs of the error amplifier. The SS pin must reach approximately 0.65 V before the input to the error amplifier begins to rise above 0 V. To charge the SS pin from 0 V to 0.65 V faster, an extra charging current (40.4 µA, typical.) is switched-in to the SS pin at the beginning of the soft-start in addition to the normal charging current (11.6 µA, typical.). As the SS capacitor reaches 0.5 V, the extra charging current is turned off and only the normal charging current remains. Figure 6-5 shows the soft-start function block.

GUID-70C9E1A3-0FE0-4F67-8410-2329645E9610-low.gifFigure 6-5 Soft-Start Schematic Block

As the SS pin voltage approaches 0.65 V, the positive input to the error amplifier begins to rise (see Figure 6-6). The output of the error amplifier (the COMP pin) starts rising. The rate of rise of the COMP voltage is mainly limited by the feedback-loop compensation network. Once VCOMP reaches the Vvalley of the PWM ramp, the switching begins. The output is regulated to the error amplifier input through the FB pin in the feedback loop. Once the FB pin reaches the 600-mV reference voltage, the feedback node is regulated to the reference voltage, VREF. The SS pin continues to rise and is clamped to VDD.

The SS pin is discharged through an internal switch during the following conditions:

  • Input (VIN) undervoltage lock out UVLO pin less than VUVLO
  • Overcurrent protection calibration time (tCAL)
  • VBP less than threshold voltage (VBP(off))

Because it is discharged through an internal switch, the discharging time is relatively fast compared with the discharging time during the fault restart, which is discussed in the Section 6.3.7.1 section.

GUID-7BF68286-5BB8-4135-ADFB-6D6ED43D6FC4-low.gifFigure 6-6 Soft-Start Waveforms
Note:

Referring to Figure 6-6:

(1) VREF dominates the positive input of the error amplifier.

(2) SS_EAMP dominates the positive input of the error amplifier.

For 0 < VSS_EAMP < VREF

Equation 8. GUID-E6783E7F-69A7-4B7E-B4CB-18A0FCA45693-low.gif

For VSS_EAMP > VREF

Equation 9. GUID-29CED092-ED19-4868-9B70-ACE8ADA1CD0D-low.gif